Hole Mobility Enhancement Caused by Gate-Induced Vertical Strain in Gate-First Full-Metal High-$k$ P-Channel Field Effect Transistors Using Ion-Beam W

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In this paper, we describe a new technique of enhancing hole mobility in full-metal high-$k$ p-channel field effect transistors (pFETs) constructed by a conventional gate-first process. A tungsten layer used as a low-resistivity gate creates a global tensile strain when it is deposited by physical vapor deposition (PVD). After the gate patterning, however, the stress in the tungsten gate modulates the local strain in the channel. If it is deposited by ion-beam PVD, the tungsten layer has a small amount of compressive stress, and does not relax the wafer-level global strain created in the W-deposition step, and eventually creates a local tensile strain after gate patterning in the horizontal (source-to-drain) and vertical (gate-to-substrate) directions. In contrast, if it is deposited by conventional PVD, the large amount of compressive stress in the tungsten gate creates a small amount of local compressive strain in the horizontal and vertical directions after gate patterning. Since the vertical tensile strain created by the ion-beam-deposited tungsten gate increases the drain current of pFETs, it can be used as a cost-effective stress memorization technique to enhance device performance.
2009-05-25