Dual-Metal Gate Technology with Metal-Inserted Full Silicide Stack and Ni-Rich Full Silicide Gate Electrodes Using a Single Ni-Rich Full Silicide Phase for Scaled High-$k$ Complementary Metal–Oxide–Semiconductor Field-Effect Transistors

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概要

• 論文の詳細を見る

• A new dual-metal-gate technology that includes a metal-inserted full silicide stack (MIFS) is proposed for scaled high-$k$ complementary metal–oxide–semiconductor (CMOS) processes. A single Ni-rich full silicide (FUSI) layer is used for both types of MOS field-effect transistors (MOSFETs) without the need to form two different FUSI phases, while a thin-TiN layer is selectively inserted between Ni-rich FUSI and a high-$k$ material only for n-channel MOSFETs (nMOSFETs). A low effective work function ($\phi_{\text{m,eff}}$) of 4.45 eV can be obtained in HfSiON nMOSFETs using MIFS gate electrodes whose structure is Ni-rich FUSI/thin TiN (2 nm). $\phi_{\text{m,eff}}$ of Ni-rich FUSI gate electrodes fabricated after the selective removal of TiN from HfSiON is as high as 4.8 eV in HfSiON p-channel MOSFETs (pMOSFETs), which is similar to that obtained for ‘control’ Ni-rich FUSI gate electrodes. Since $\phi_{\text{m,eff}}$ remains unchanged with decreasing equivalent oxide thickness (EOT), this dual-metal-gate technology is promising for use in scaled high-$k$ CMOS processes from the viewpoints of $\phi_{\text{m,eff}}$, process compatibility, mobility, and EOT scaling.

• 2009-04-25

著者

• Matsuki Takeo

  Semiconductor Leading Edge Technologies Inc. (selete)

• Ohji Yuzuru

  Semiconductor & Integrated Circuits Division Hitachi Ltd.

• Nara Yasuo

  Semiconductor Leading Edge Technologies Inc.

• Aoyama Takayuki

  Semiconductor Leading Edge Technologies Inc.

• Kadoshima Masaru

  Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan

• Ohji Yuzuru

  Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan

• Aminaka Toshio

  Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan

• Kurosawa Etsuo

  Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan

• Kitajima Masashi

  Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan

• Kurosawa Etsuo

  Semiconductor Leading Edge Technologies (Selete), Inc., Tsukuba, Ibaraki 305-8569, Japan

• Aminaka Toshio

  Semiconductor Leading Edge Technologies (Selete), Inc., Tsukuba, Ibaraki 305-8569, Japan

• Kadoshima Masaru

  Semiconductor Leading Edge Technologies (Selete), Inc., Tsukuba, Ibaraki 305-8569, Japan

• Aoyama Takayuki

  Semiconductor Leading Edge Technologies (Selete), Inc., Tsukuba, Ibaraki 305-8569, Japan

関連論文

• Evaluation of Dielectric Reliability of Ultrathin HfSiO_xN_y in Metal-Gate Capacitors(Ultra-Thin Gate Insulators,Fundamentals and Applications of Advanced Semiconductor Devices)
• High-resolution RBS analysis of Si-dielectrics interfaces
• Comprehensive Understanding of PBTI and NBTI reliability of High-k / Metal Gate Stacks with EOT Scaling to sub-1nm
• Hf and N Release from HfSiON in High-Temperature Annealing Induced by Oxygen Incorporation
• Mechanism of Threshold Voltage Reduction and Hole Mobility Enhancement in pMOSFETs Employing Sub-1nm EOT HfSiON by Use of Substrate Fluorine Ion Implantation
• Extendibility of High Mobility HfSiON Gate Dielectrics
• Thermal Degradation of HfSiON Dielectrics Caused by TiN Gate Electrodes and Its Impact on Electrical Properties
• Properties of Ruthenium Films Prepared by Liquid Source Metalorganic Chemical Vapor Deposition Using Ru(EtCp)_2 with Tetrahydrofuran Solvent
• Gate-Last MISFET Structures and Process for Characterization of High-k and Metal Gate MISFETs(Microelectronic Test Structures)
• Performance and Reliability Improvement by Optimized Nitrogen Content of TaSiNx Metal Gate in Metal/HfSiON nFETs
• Area Selective Flash Lamp Post-Deposition Annealing of High-k Film Using Si Photo Absorber for Metal Gate MISFETs with NiSi Source/Drain
• Study of a Negative Threshold Voltage Shift in Positive Bias Temperature Instability and a Positive Threshold Voltage Shift the Negative Bias Temperature Instability of Yttrium-Doped HfO2 Gate Dielectrics
• Impact of Activation Annealing Temperature on the Performance, Negative Bias Temperature Instability, and Time-to-Dielectric Breakdown Lifetime of High-$k$/Metal Gate Stack p-Type Metal–Oxide–Semiconductor Field Effect Transistors
• Improvement of Device Characteristics for TiN Gate p-Type Metal–Insulator–Semiconductor Field-Effect Transistor with Al2O3-Capped HfO2 Dielectrics by Controlling Al2O3 Diffusion Annealing Process
• Dual-Metal Gate Technology with Metal-Inserted Full Silicide Stack and Ni-Rich Full Silicide Gate Electrodes Using a Single Ni-Rich Full Silicide Phase for Scaled High-$k$ Complementary Metal–Oxide–Semiconductor Field-Effect Transistors
• Etch Profile Control of W/TiN/HfSiON and W/TaSiN/HfSiON Full-Metal Gates
• Suppression of Metamorphoses of Metal/High-$k$ Gate Stack by Low-Temperature, Cl-Free SiN Offset Spacer, and Its Impact on Scaled Metal–Oxide–Semiconductor Field-Effect Transistors
• Hole Mobility Enhancement Caused by Gate-Induced Vertical Strain in Gate-First Full-Metal High-$k$ P-Channel Field Effect Transistors Using Ion-Beam W
• Hafnium 4f Core-level Shifts Caused by Nitrogen Incorporation in Hf-based High-$k$ Gate Dielectrics
• Characterization of Metal/High-$k$ Structures Using Monoenergetic Positron Beams
• Guiding Principle of Energy Level Controllability of Silicon Dangling Bonds in HfSiON
• Cathode Electron Injection Breakdown Model and Time Dependent Dielectric Breakdown Lifetime Prediction in High-$k$/Metal Gate Stack p-Type Metal–Oxide–Silicon Field Effect Transistors
• Impact of High Temperature Annealing on Traps in Physical-Vapor-Deposited-TiN/SiO2/Si Analyzed by Positron Annihilation
• Origin of the Hole Current in n-type High-$k$/Metal Gate Stacks Field Effect Transistor in an Inversion State
• Trap-Related Carrier Transports in p-Channel Field-Effect Transistor with Polycrystalline Si/HSiON Gate Stack
• Comprehensive Analysis of Positive and Negative Bias Temperature Instabilities in High-$k$/Metal Gate Stack Metal–Oxide–Silicon Field Effect Transistors with Equivalent Oxide Thickness Scaling to Sub-1 nm
• Modified Oxygen Vacancy Induced Fermi Level Pinning Model Extendable to P-Metal Pinning
• Thermal Degradation of HfSiON Dielectrics Caused by TiN Gate Electrodes and Its Impact on Electrical Properties
• Universal Correlation between Flatband Voltage and Electron Mobility in TiN/HfSiON Devices with MgO or La2O3 Incorporation and Stack Variation
• Performance and Reliability Improvement by Optimizing the Nitrogen Content of the TaSiNx Metal Gate in Metal/HfSiON n-Type Field-Effect Transistors
• Impact on Performance, Positive Bias Temperature Instability, and Time-Dependent Dielectric Dreakdown of n-Type Field Effect Transistors Incorporating Mg into HfSiON Gate Dielectrics
• Thermally Unstable Ruthenium Oxide Gate Electrodes in Metal/High-$k$ Gate Stacks
• Fabrication of High-Mobility Nitrided Hafnium Silicate Gate Dielectrics with Sub-1-nm Equivalent Oxide Thickness Using Plasma Nitridation and High-Temperature Postnitridation Annealing
• Impact of Gate Metal-Induced Stress on Performance Modulation in Gate-Last Metal–Oxide–Semiconductor Field-Effect Transistors

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