Gate-Last MISFET Structures and Process for Characterization of High-k and Metal Gate MISFETs(<Special Section>Microelectronic Test Structures)

スポンサーリンク

概要

• 論文の詳細を見る

• We propose new test device structures, Gate-Last-formed structures, which are suitable for fundamental study of high-k gate insulator or metal gate electrode MISFETs. The gate insulator and electrode stack is formed after local interconnect pads connected with source and drain. The gate stack is build in trench formed by dry and wet etching and is non-self-aligned to the source and drain. The wet etching restricts damage formation on the exposed Si surface underneath the trench. Electrical characteristics are measurable just after exposure of surface of the local interconnect pads without conventional Al wiring. This structure can provide methods both for fundamental evaluation and for material selection of new gate stack materials by investigation of MISFET characteristics. This is achieved with short TAT and avoiding contamination penalty to a fab.

• 社団法人電子情報通信学会の論文
• 2005-05-01

著者

• TORII Kazuyoshi

  Semiconductor Leading Edge Technologies, Inc.

• Matsuki Takeo

  Semiconductor Leading Edge Technologies Inc. (selete)

• MATSUKI Takeo

  Research Department 1, Semiconductor Leading Edge Technologies, Inc.

• AKASAKA Yasushi

  Semiconductor Leading Edge Technologies Inc.

• ARIKADO Tsunetoshi

  Semiconductor Leading Edge Technologies Inc.

• MAEDA Takeshi

  Semiconductor Leading Edge Technologies, Inc.

• Arikado Tsunetoshi

  Semiconductor Leading Edge Technologies Inc. (selete)

• Torii Kazuyoshi

  Semiconductor Leading Edge Technologies Inc.

• HAYASHI Kiyoshi

  Semiconductor Leading Edge Technologies, Inc.

• KASAI Naoki

  Semiconductor Leading Edge Technologies, Inc.

• Kasai Naoki

  Device Platforms Laboratories Nec Corporation

• Hayashi Kiyoshi

  Renesas

• Akasaka Yasushi

  Semiconductor Leading Edge Technologies Inc. (selete)

• Maeda Takeshi

  Semiconductor Leading Edge Technologies Inc.

関連論文

• Impact of Rapid Thermal O_2 Anneal on Dielectric Stack Structures of Hafnium Aluminate and Silicon Dioxide Formed on Si(100)
• High-resolution RBS analysis of Si-dielectrics interfaces
• Effect of Purge Time on the Properties of HfO_2 Films Prepared by Atomic Layer Deposition(High-κ Gate Dielectrics)
• Hf and N Release from HfSiON in High-Temperature Annealing Induced by Oxygen Incorporation
• Mechanism of Threshold Voltage Reduction and Hole Mobility Enhancement in pMOSFETs Employing Sub-1nm EOT HfSiON by Use of Substrate Fluorine Ion Implantation
• Extendibility of High Mobility HfSiON Gate Dielectrics
• Effect of Fluorine on Interface Characteristics in Low-Temperature CMIS Process with HfO_2 Metal Gate Stacks
• Effect of Fluorine on Interface Characteristics in Low-temperature CMIS Process with HfO_2 Metal Gate Stacks
• Effect of Boron and Fluorine Incorporation in SiON Gate Insulator with Optimized Nitrogen Profile
• Selective Dry Etching of HfO_2 in CF_4 and Cl_2/HBr-Based Chemistries
• Physical and Electrical Properties of HfAlO_x Films Prepared by Atomic Layer Deposition Using NH_3/Ar Plasma
• Thermal Instability of Poly-Si Gate Al_2O_3 MOSFETs
• Modified Oxygen Vacancy Induced Fermi Level Pinning Model Extendable to P-Metal Pinning
• Thermal Degradation of HfSiON Dielectrics Caused by TiN Gate Electrodes and Its Impact on Electrical Properties
• Oxygen Vacancy Induced Substantial Threshold Voltage Shifts in the Hf-based High-K MISFET with p+poly-Si Gates : A Theoretical Approach
• MRAM Applications Using Unlimited Write Endurance(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
• Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode(Integrated Electronics)
• Characterization of Hf_Al_O_x Fabricated by Atomic-Layer-Deposition Technique Using Monoenergetic Positron Beams
• Role of Nitrogen Incorporation into Hf-Based High-k Gate Dielectrics for Termination of Local Current Leakage Paths
• Effect of Purge Time on the Properties of HfO_2 Films Prepared by Atomic Layer Deposition
• Gate-Last MISFET Structures and Process for Characterization of High-k and Metal Gate MISFETs(Microelectronic Test Structures)
• Effect of Hf Sources, Oxidizing Agents, and NH_3/Ar Plasma on the Properties of HfAlO_x Films Prepared by Atomic Layer Deposition
• Improvement of Thermal Stability of MRAM Device with SiN Protective Film Deposited by HDP CVD
• Nitrogen profile engineering in the interfacial SiON for HfAlOx gate dielectric
• Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond
• Improvements of Electrical Properties with Reduced Transient-Enhanced-Diffusion for 65nm-node CMOS Technology using Flash Lamp Annealing
• Area Selective Flash Lamp Post-Deposition Annealing of High-k Film Using Si Photo Absorber for Metal Gate MISFETs with NiSi Source/Drain
• Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros
• Study of a Negative Threshold Voltage Shift in Positive Bias Temperature Instability and a Positive Threshold Voltage Shift the Negative Bias Temperature Instability of Yttrium-Doped HfO2 Gate Dielectrics
• Improvement of Device Characteristics for TiN Gate p-Type Metal–Insulator–Semiconductor Field-Effect Transistor with Al2O3-Capped HfO2 Dielectrics by Controlling Al2O3 Diffusion Annealing Process
• Dual-Metal Gate Technology with Metal-Inserted Full Silicide Stack and Ni-Rich Full Silicide Gate Electrodes Using a Single Ni-Rich Full Silicide Phase for Scaled High-$k$ Complementary Metal–Oxide–Semiconductor Field-Effect Transistors
• Suppression of Metamorphoses of Metal/High-$k$ Gate Stack by Low-Temperature, Cl-Free SiN Offset Spacer, and Its Impact on Scaled Metal–Oxide–Semiconductor Field-Effect Transistors
• Characterization of Hf0.3Al0.7Ox Fabricated by Atomic-Layer-Deposition Technique Using Monoenergetic Positron Beams
• Effect of Boron and Fluorine Incorporation in SiON Gate Insulator with Optimized Nitrogen Profile
• Selective Dry Etching of HfO2 in CF4 and Cl2/HBr-Based Chemistries
• Characterization of Metal/High-$k$ Structures Using Monoenergetic Positron Beams
• Role of Nitrogen Incorporation into Hf-Based High-$k$ Gate Dielectrics for Termination of Local Current Leakage Paths
• Guiding Principle of Energy Level Controllability of Silicon Dangling Bonds in HfSiON
• Transient Capacitance in Metal-Oxide-Semiconductor Structures with Stacked Gate Dielectrics
• Impact of High Temperature Annealing on Traps in Physical-Vapor-Deposited-TiN/SiO2/Si Analyzed by Positron Annihilation
• Modified Oxygen Vacancy Induced Fermi Level Pinning Model Extendable to P-Metal Pinning
• Effect of Hf Sources, Oxidizing Agents, and NH3/Ar Plasma on the Properties of HfAlOx Films Prepared by Atomic Layer Deposition
• Thermal Degradation of HfSiON Dielectrics Caused by TiN Gate Electrodes and Its Impact on Electrical Properties
• Impact of Rapid Thermal O2 Anneal on Dielectric Stack Structures of Hafnium Aluminate and Silicon Dioxide Formed on Si(100)
• Physical and Electrical Properties of HfAlOx Films Prepared by Atomic Layer Deposition Using NH3/Ar Plasma
• Fabrication of High-Mobility Nitrided Hafnium Silicate Gate Dielectrics with Sub-1-nm Equivalent Oxide Thickness Using Plasma Nitridation and High-Temperature Postnitridation Annealing
• Impact of Gate Metal-Induced Stress on Performance Modulation in Gate-Last Metal–Oxide–Semiconductor Field-Effect Transistors

もっと見る 閉じる

スポンサーリンク