Thermal Degradation of HfSiON Dielectrics Caused by TiN Gate Electrodes and Its Impact on Electrical Properties

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概要

• 論文の詳細を見る

• We studied thermal reactions in TiN/HfSiON gate stacks and discussed their impact on electrical properties. Physical analysis revealed that reactions at the metal/high-$k$ interface form a polycrystalline TiO2 layer at 700 °C. The interface between the TiN electrode and the ultrathin TiO2 interlayer remained smooth and the formation of this high-permittivity metal oxide layer did not cause any electrical degradation in terms of equivalent oxide thickness (EOT) versus gate leakage ($I_{\text{g}}$) characteristics. However, interface roughness and electrical degradation, such as increases in electrical thickness and interface-trap density, were present after annealing at 900 °C. At 1100 °C, we observed marked increases in EOT and $I_{\text{g}}$, which respectively indicated oxide (SiO2) growth at the bottom interface and dielectric degradation both of the interface TiO2 and HfSiON layers.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2006-04-30

著者

• Yasutake Kiyoshi

  Department Of Material And Life Science Graduate School Of Engineering Osaka University

• AKASAKA Yasushi

  Semiconductor Leading Edge Technologies Inc.

• Watanabe Heiji

  Department Of Material And Life Science Graduate School Of Engineering Osaka University

• Watanabe Yasumasa

  Department Of Chemical Pharmacology Faculty Of Pharmaceutical Sciences The University Of Tokyo

• Nara Yasuo

  Semiconductor Leading Edge Technologies Inc.

• Yamada Keisaku

  Nanotechnology Research Laboratories Waseda University

• Yoshida Shiniti

  Department Of Precision Science And Technology Graduate School Of Engineering Osaka University

• Shimura Takayoshi

  Department Of Material And Life Science Graduate School Of Engineering Osaka University

• Nakamura Kunio

  Semiconductor Leading Edge Technologies Inc.

• Akasaka Yasushi

  Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki 305-8569, Japan

• Shimura Takayoshi

  Department of Precision Science and Technology, Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871, Japan

• Watanabe Yasumasa

  Department of Precision Science and Technology, Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871, Japan

• Nakamura Kunio

  Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki 305-8569, Japan

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