Impact of Activation Annealing Temperature on the Performance, Negative Bias Temperature Instability, and Time-to-Dielectric Breakdown Lifetime of High-$k$/Metal Gate Stack p-Type Metal–Oxide–Semiconductor Field Effect Transistors
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概要
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We have clarified the effects of activation annealing temperature on the negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) lifetime improvement of HfSiON/TiN gate stack p-type metal–oxide–semiconductor field effect transistors. Higher-temperature annealing is effective for the improvement in NBTI and TDDB lifetime. This is due to the Si substrate oxidation occuring during the high-temperature annealing, resulting in interface defect state reduction. Annealing is also effective for reducing threshold voltage with consequential improvement in device performance.
- 2009-04-25
著者
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Ohji Yuzuru
Semiconductor & Integrated Circuits Division Hitachi Ltd.
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Nara Yasuo
Semiconductor Leading Edge Technologies Inc.
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Sato Motoyuki
Semiconductor Leading Edge Technologies Inc. (selete)
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Aoyama Takayuki
Semiconductor Leading Edge Technologies Inc.
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Ohji Yuzuru
Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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Aoyama Takayuki
Semiconductor Leading Edge Technologies (Selete), Inc., Tsukuba, Ibaraki 305-8569, Japan
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