Ohji Yuzuru | Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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概要
- Ohji Yuzuruの詳細を見る
- 同名の論文著者
- Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japanの論文著者
関連著者
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Ohji Yuzuru
Semiconductor & Integrated Circuits Division Hitachi Ltd.
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Nara Yasuo
Semiconductor Leading Edge Technologies Inc.
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Aoyama Takayuki
Semiconductor Leading Edge Technologies Inc.
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Ohji Yuzuru
Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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Aoyama Takayuki
Semiconductor Leading Edge Technologies (Selete), Inc., Tsukuba, Ibaraki 305-8569, Japan
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Sato Motoyuki
Semiconductor Leading Edge Technologies Inc. (selete)
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Eimori Takahisa
Semiconductor Leading Edge Technologies Inc.
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Matsuki Takeo
Semiconductor Leading Edge Technologies Inc. (selete)
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Onizawa Takashi
Semiconductor Leading Edge Technologies Inc.
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Eimori Takahisa
Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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Kadoshima Masaru
Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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Aminaka Toshio
Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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Kurosawa Etsuo
Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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Kitajima Masashi
Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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Kurosawa Etsuo
Semiconductor Leading Edge Technologies (Selete), Inc., Tsukuba, Ibaraki 305-8569, Japan
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Aminaka Toshio
Semiconductor Leading Edge Technologies (Selete), Inc., Tsukuba, Ibaraki 305-8569, Japan
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Kadoshima Masaru
Semiconductor Leading Edge Technologies (Selete), Inc., Tsukuba, Ibaraki 305-8569, Japan
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Onizawa Takashi
Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
著作論文
- Impact of Activation Annealing Temperature on the Performance, Negative Bias Temperature Instability, and Time-to-Dielectric Breakdown Lifetime of High-$k$/Metal Gate Stack p-Type Metal–Oxide–Semiconductor Field Effect Transistors
- Dual-Metal Gate Technology with Metal-Inserted Full Silicide Stack and Ni-Rich Full Silicide Gate Electrodes Using a Single Ni-Rich Full Silicide Phase for Scaled High-$k$ Complementary Metal–Oxide–Semiconductor Field-Effect Transistors
- Performance and Reliability Improvement by Optimizing the Nitrogen Content of the TaSiNx Metal Gate in Metal/HfSiON n-Type Field-Effect Transistors