Area Selective Flash Lamp Post-Deposition Annealing of High-k Film Using Si Photo Absorber for Metal Gate MISFETs with NiSi Source/Drain

スポンサーリンク

概要

論文の詳細を見る
2005-09-13

著者

関連論文

Evaluation of Dielectric Reliability of Ultrathin HfSiO_xN_y in Metal-Gate Capacitors(Ultra-Thin Gate Insulators,Fundamentals and Applications of Advanced Semiconductor Devices)
High-resolution RBS analysis of Si-dielectrics interfaces
Comprehensive Understanding of PBTI and NBTI reliability of High-k / Metal Gate Stacks with EOT Scaling to sub-1nm
Hf and N Release from HfSiON in High-Temperature Annealing Induced by Oxygen Incorporation
Mechanism of Threshold Voltage Reduction and Hole Mobility Enhancement in pMOSFETs Employing Sub-1nm EOT HfSiON by Use of Substrate Fluorine Ion Implantation
Extendibility of High Mobility HfSiON Gate Dielectrics
Effect of Fluorine on Interface Characteristics in Low-Temperature CMIS Process with HfO_2 Metal Gate Stacks
Effect of Fluorine on Interface Characteristics in Low-temperature CMIS Process with HfO_2 Metal Gate Stacks
Modified Oxygen Vacancy Induced Fermi Level Pinning Model Extendable to P-Metal Pinning
Thermal Degradation of HfSiON Dielectrics Caused by TiN Gate Electrodes and Its Impact on Electrical Properties
Oxygen Vacancy Induced Substantial Threshold Voltage Shifts in the Hf-based High-K MISFET with p+poly-Si Gates : A Theoretical Approach
MRAM Applications Using Unlimited Write Endurance(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode(Integrated Electronics)
Production-Worthy HfSiON Gate Dielectric Fabrication Enabling EOT Scalability Down to 0.86nm and Excellent Reliability by Polyatomic Layer Chemical Vapor Deposition Technique
Quantum Mechanical Analysis of Accumulation Layers in MOS Structures
Gate-Last MISFET Structures and Process for Characterization of High-k and Metal Gate MISFETs(Microelectronic Test Structures)
Performance and Reliability Improvement by Optimized Nitrogen Content of TaSiNx Metal Gate in Metal/HfSiON nFETs
Improvement of Thermal Stability of MRAM Device with SiN Protective Film Deposited by HDP CVD
Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond
Area Selective Flash Lamp Post-Deposition Annealing of High-k Film Using Si Photo Absorber for Metal Gate MISFETs with NiSi Source/Drain
Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros
Study of a Negative Threshold Voltage Shift in Positive Bias Temperature Instability and a Positive Threshold Voltage Shift the Negative Bias Temperature Instability of Yttrium-Doped HfO2 Gate Dielectrics
Impact of Activation Annealing Temperature on the Performance, Negative Bias Temperature Instability, and Time-to-Dielectric Breakdown Lifetime of High-$k$/Metal Gate Stack p-Type Metal–Oxide–Semiconductor Field Effect Transistors
Improvement of Device Characteristics for TiN Gate p-Type Metal–Insulator–Semiconductor Field-Effect Transistor with Al2O3-Capped HfO2 Dielectrics by Controlling Al2O3 Diffusion Annealing Process
Dual-Metal Gate Technology with Metal-Inserted Full Silicide Stack and Ni-Rich Full Silicide Gate Electrodes Using a Single Ni-Rich Full Silicide Phase for Scaled High-$k$ Complementary Metal–Oxide–Semiconductor Field-Effect Transistors
Etch Profile Control of W/TiN/HfSiON and W/TaSiN/HfSiON Full-Metal Gates
Suppression of Metamorphoses of Metal/High-$k$ Gate Stack by Low-Temperature, Cl-Free SiN Offset Spacer, and Its Impact on Scaled Metal–Oxide–Semiconductor Field-Effect Transistors
Hole Mobility Enhancement Caused by Gate-Induced Vertical Strain in Gate-First Full-Metal High-$k$ P-Channel Field Effect Transistors Using Ion-Beam W
Extended Scalability of HfON/SiON Gate Stack Down to 0.57 nm Equivalent Oxide Thickness with High Carrier Mobility by Post-Deposition Annealing
Hafnium 4f Core-level Shifts Caused by Nitrogen Incorporation in Hf-based High-$k$ Gate Dielectrics
Characterization of Metal/High-$k$ Structures Using Monoenergetic Positron Beams
Interfacial Reaction of TiN/HfSiON Gate Stack in High-Temperature Annealing for Gate-First Metal–Oxide–Semiconductor Field-Effect Transistors
Guiding Principle of Energy Level Controllability of Silicon Dangling Bonds in HfSiON
Cathode Electron Injection Breakdown Model and Time Dependent Dielectric Breakdown Lifetime Prediction in High-$k$/Metal Gate Stack p-Type Metal–Oxide–Silicon Field Effect Transistors
Impact of High Temperature Annealing on Traps in Physical-Vapor-Deposited-TiN/SiO2/Si Analyzed by Positron Annihilation
Origin of the Hole Current in n-type High-$k$/Metal Gate Stacks Field Effect Transistor in an Inversion State
Trap-Related Carrier Transports in p-Channel Field-Effect Transistor with Polycrystalline Si/HSiON Gate Stack
Comprehensive Analysis of Positive and Negative Bias Temperature Instabilities in High-$k$/Metal Gate Stack Metal–Oxide–Silicon Field Effect Transistors with Equivalent Oxide Thickness Scaling to Sub-1 nm
Modified Oxygen Vacancy Induced Fermi Level Pinning Model Extendable to P-Metal Pinning
Thermal Degradation of HfSiON Dielectrics Caused by TiN Gate Electrodes and Its Impact on Electrical Properties
Area-Selective Post-Deposition Annealing Process Using Flash Lamp and Si Photoenergy Absorber for Metal/High-$k$ Gate Metal–Insulator–Semiconductor Field-Effect Transistors with NiSi Source/Drain
Universal Correlation between Flatband Voltage and Electron Mobility in TiN/HfSiON Devices with MgO or La2O3 Incorporation and Stack Variation
Performance and Reliability Improvement by Optimizing the Nitrogen Content of the TaSiNx Metal Gate in Metal/HfSiON n-Type Field-Effect Transistors
Impact on Performance, Positive Bias Temperature Instability, and Time-Dependent Dielectric Dreakdown of n-Type Field Effect Transistors Incorporating Mg into HfSiON Gate Dielectrics
Thermally Unstable Ruthenium Oxide Gate Electrodes in Metal/High-$k$ Gate Stacks
Fabrication of High-Mobility Nitrided Hafnium Silicate Gate Dielectrics with Sub-1-nm Equivalent Oxide Thickness Using Plasma Nitridation and High-Temperature Postnitridation Annealing
Impact of Gate Metal-Induced Stress on Performance Modulation in Gate-Last Metal–Oxide–Semiconductor Field-Effect Transistors

もっと見る

スポンサーリンク