Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros
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概要
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We propose an MRAM macro architecture for SoCs to reduce their area size. The shared write-selection transistor (SWST) architecture is based on 2T1MTJ MRAM cell technology, which enables the same fast access time with a smaller cell area than that of 6T SRAMs. We designed a 4-Mb macro using the SWST architecture with a 0.15-µm CMOS process and a 0.24-µm MRAM process. The macro cell array consists of 81T64MTJ cell array elements, each storing 64bits of data. The area size is reduced by more than 30%. By introducing a leakage-replication (LR) read scheme, a wide read margin on a test chip is accomplished and 50-ns access time is achieved with SPICE simulation. The 2T1MTJ macro and 81T64MTJ macro can be integrated into a single SoC.
- 2009-04-01
著者
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Sakimura Noboru
System Devices Research Laboratories Nec Corporation
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Sakimura Noboru
Device Platforms Laboratories Nec Corporation
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Kasai Naoki
Device Platforms Laboratories Nec Corporation
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Sugibayashi T
Device Platforms Laboratories Nec Corporation
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Nebashi Ryusuke
Device Platforms Laboratories Nec Corporation
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SUGIBAYASHI Tadahiko
Device Platforms Laboratories, NEC Corporation
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Sugibayashi Tadahiko
Nec Corporation Device Platforms Research Laboratories
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Sugibayashi Tadahiko
Device Platforms Laboratories Nec Corporation
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