A Distributive Serial Multi-Bit Parallel Test Scheme for Large Capacity DRAMs (Special Section on High Speed and High Density Multi Functional LSI Memories)

概要

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A distributive serial multi-bit parallel test scheme for large capacity DRAMs has been developed. The scheme, distributively and serially, extracts and compares the data from cells on a main word-line. This test scheme features a high parallel test bit number, little restriction on test patterns, and, with regard to cells and sense-amplifiers, the same operational margin as normal mode. In an experimental 256-Mb DRAM, the scheme successfully has achieved a 512-bit parallel test.
社団法人電子情報通信学会の論文
1994-08-25