A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs (Special Issue on ULSI Memory Technology)

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概要

• 論文の詳細を見る

• A crossing charge recycle refresh (CCRR) scheme and a serial charge recycle refresh (SCRR) scheme are proposed for the large capacity DRAMs with hierarchical bit-line architecture to reduce main bit-line charging current. A separated driver sense-amplifier (SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense-amplitiers. These circuits are applied to an experimental 1-Gb DRAM, which achieves reduction of main bit-line charging current to 37.5 %.

• 社団法人電子情報通信学会の論文
• 1996-06-25

著者

• Murotani Tatsunori

  Ulsi Device Development Laboratories Nec Corporation

• Utsugi S

  Ulsi Device Development Laboratories Nec Corporation

• Sugibayashi T

  Device Platforms Laboratories Nec Corporation

• Sugibayashi Tadahiko

  Ulsi Device Development Laboratories Nec Corporation

• NARITAKE Isao

  ULSI Device Development Laboratories, NEC Corporation

• UTSUGI Satoshi

  ULSI Device Development Laboratories, NEC Corporation

• Naritake Isao

  Ulsi Device Development Laboratories Nec Corporation

• Sugibayashi Tadahiko

  Nec Corporation Device Platforms Research Laboratories

• Utsugi Satoshi

  Ulsi Device Development Laboratories Nec Corporation

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• Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode(Integrated Electronics)
• MRAM Writing Circuitry to Compensate for Thermal Variation of Magnetization Reversal Current
• Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme
• Improvement of Thermal Stability of MRAM Device with SiN Protective Film Deposited by HDP CVD
• Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros
• Hierarchical Word-Line Architecture for Large Capacity DRAMs (Special Issue on Circuit Technologies for Memory and Analog LSIs)
• A Distributive Serial Multi-Bit Parallel Test Scheme for Large Capacity DRAMs (Special Section on High Speed and High Density Multi Functional LSI Memories)
• A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs (Special Issue on ULSI Memory Technology)
• Improvement of Thermal Stability of Magnetoresistive Random Access Memory Device with SiN Protective Film Deposited by High-Density Plasma Chemical Vapor Deposition

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