Area-Selective Post-Deposition Annealing Process Using Flash Lamp and Si Photoenergy Absorber for Metal/High-$k$ Gate Metal–Insulator–Semiconductor Field-Effect Transistors with NiSi Source/Drain
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概要
- 論文の詳細を見る
We have proposed an area-selective post-deposition annealing (PDA) process that involves a combination of flash lamp annealing and the use of a Si photoenergy absorber (Si-PEA) for metal/high-$k$ gate last metal–insulator–semiconductor field-effect transistors (MISFETs) with NiSi on source/drain (S/D). The process makes it possible to suppress the increase in both the sheet resistance and junction leakage current of NiSi S/D regions. This PDA process also showed optimality for silicide gate electrode formation with silicidation of part of the Si-PEA. It was found that the flash lamp PDA with Si-PEA on nickel–silicide/HfAlOx/SiO2 gate-last MISFETs reduced electron trapping at the gate dielectric and resulted in better PBTI immunity than conventional rapid thermal PDA and flash lamp PDA without Si-PEA.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2006-04-30
著者
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NARA Yasuo
Research Department 1, Semiconductor Leading Edge Technologies, Inc.
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TORII Kazuyoshi
Research Department 1, Semiconductor Leading Edge Technologies, Inc. (SELETE)
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Akasaka Yasushi
Research Department 1 Semiconductor Leading Edge Technologies Inc.
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Matsuki Takeo
Research Department 1 Semiconductor Leading Edge Technologies Inc.
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YAMASHITA KOJI
Research and Technology Development Division, HSP company
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Yamashita Koji
Research Department 1, Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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Akasaka Yasushi
Research Department 1, Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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Nishimura Isamu
Research Department 1, Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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Hayashi Kiyoshi
Research Department 1, Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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Noguchi Masataka
Research Department 1, Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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Kasai Naoki
Research Department 1, Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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Matsuki Takeo
Research Department 1, Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
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- Area-Selective Post-Deposition Annealing Process Using Flash Lamp and Si Photoenergy Absorber for Metal/High-$k$ Gate Metal–Insulator–Semiconductor Field-Effect Transistors with NiSi Source/Drain
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