Ni-Salicided Poly-Si/poly-SiGe-Layered Gate Technology for 65-nm-node CMOSFETs
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概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2004-04-30
著者
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Muto Akiyoshi
Research Department 1 Semiconductor Leading Edge Technologies Inc. (selete)
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Maeda Takeshi
Research Department 1 Semiconductor Leading Edge Technologies Inc. (selete)
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Ohji Hiroshi
Research Department 1 Semiconductor Leading Edge Technologies Inc. (selete)
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KITAJIMA Hiroshi
Research Dept. 1, Semiconductor Leading Edge Technologies (Selete), Inc.
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TORII Kazuyoshi
Research Department 1, Semiconductor Leading Edge Technologies, Inc. (SELETE)
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