Extended Scalability of HfON/SiON Gate Stack Down to 0.57 nm Equivalent Oxide Thickness with High Carrier Mobility by Post-Deposition Annealing

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We discuss scaling the equivalent oxide thickness (EOT) of Hf-based high-$k$ gate dielectrics by post-deposition annealing (PDA). Thin HfON/SiON gate stacks with $\mathrm{EOT}=0.57$ nm were successfully formed by repeating ultra thin (0.6 nm) HfO2 deposition and high-temperature (950 °C) PDA on a previously formed SiON interfacial layer. Physical and electrical analyses revealed that the reduction in EOT was due to crystallization of HfON to the tetragonal phase which has a higher dielectric constant than the amorphous and other crystalline phases. It was also found that Hf diffusion in the SiON interfacial layer was induced by the high-temperature PDA treatment. This also improved the $k$-value of the interfacial layer and enabled aggressive scaling even when using a SiO2-based interfacial layer. The electron mobility of the gate stack is higher than those in the previous reports, indicating that a high quality interface is realized using this approach. The reduction in EOT together with the excellent interfacial quality demonstrated in the present study shows that this technique is a promising solution for the 22-nm-node and beyond.
2009-04-25