Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond

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概要

• 論文の詳細を見る

• Boron penetration from the poly-silicon gate to the silicon substrate through gate dielectrics is a crucial problem in the dual gate complementary metal-oxide semiconductor (CMOS) process. Therefore, the plasma nitridation technique has been studied well, and it has succeeded to suppress boron penetration. However, boron penetration occurs not only from the doped poly-silicon gate but also from the substrate, and resulting in several degradations of gate-oxide characteristics. On the other hand, the boron concentration of source/drain (S/D) extension has been increasing with gate shrinkage. We found that boron penetration from the S/D extension becomes a crucial problem in gate leakage and gate-oxide integrity, particularly for nanoscale positive-channel MOS (pMOS). In this study, we examined several treatments in detail to suppress boron penetration from the S/D extension, and demonstrated that the plasma nitridation treatment after gate etching is the best solution for 65-nm node CMOS and beyond.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2005-04-15

著者

• Oda Hidekazu

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Hayashi Kiyoshi

  Renesas

• SHIGA Katsuya

  Renesas Technology Corp.

• Shiga Katsuya

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Ohji Yuzuru

  Process Technology Development Division Renesas Technology Corp.

• Hayashi Takashi

  Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam

• Yamashita Tomohiro

  Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam

• Eimori Takahisa

  Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam

• Inuishi Masahide

  Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam

• Ohji Yuzuru

  Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam

• Eimori Takahisa

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Ohji Yuzuru

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Inuishi Masahide

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Hayashi Kiyoshi

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Yamashita Tomohiro

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Hayashi Takashi

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Oda Hidekazu

  Renesas Electronics Corporation, Hitachinaka, Ibaraki 312-8504, Japan

• Yamashita Tomohiro

  Renesas Electronics Corporation, Hitachinaka, Ibaraki 312-8504, Japan

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• V_/E_-Driven Breakdown of Ultrathin SiON Gate Dielectrics in p-Type Metal Oxide Semiconductor Field Effect Transistors under Low-Voltage Inversion Stress
• Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond
• Area Selective Flash Lamp Post-Deposition Annealing of High-k Film Using Si Photo Absorber for Metal Gate MISFETs with NiSi Source/Drain
• Analytical Approach for Enhancement of n-Channel Metal--Oxide--Semiconductor Field-Effect Transistor Performance with Carbon-Doped Source/Drain Formed by Molecular Carbon Ion Implantation and Laser Annealing
• $V_{\text{ox}}/E_{\text{ox}}$-Driven Breakdown of Ultrathin SiON Gate Dielectrics in p-Type Metal Oxide Semiconductor Field Effect Transistors under Low-Voltage Inversion Stress
• Evaluation of Threshold-Voltage Variation in Silicon on Thin Buried Oxide Complementary Metal–Oxide–Semiconductor and Its Impact on Decreasing Standby Leakage Current
• Investigation and Integration of Polycrystalline Silicon/TiN/SiON Gate Stack in Silicon on Thin Buried Oxide Complementary Metal Oxide Semiconductor Field Effect Transistors
• Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45 nm Node Devices and Beyond

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