SHIGA Katsuya | Renesas Technology Corp.
スポンサーリンク
概要
関連著者
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SHIGA Katsuya
Renesas Technology Corp.
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Umeda Hiroshi
Renesas Technology Corp.
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Yugami Jiro
Renesas Technology Corp.
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TSUJIKAWA Shimpei
Renesas Technology Corp.
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Oda Hidekazu
Renesas Technology Corporation Wafer Process Engineering Development Department
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Hayashi Kiyoshi
Renesas
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Shiga Katsuya
Renesas Technology Corporation Wafer Process Engineering Development Department
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Ohji Yuzuru
Process Technology Development Division Renesas Technology Corp.
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Hayashi Takashi
Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam
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Yamashita Tomohiro
Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam
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Eimori Takahisa
Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam
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Inuishi Masahide
Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam
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Ohji Yuzuru
Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam
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Eimori Takahisa
Renesas Technology Corporation Wafer Process Engineering Development Department
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Ohji Yuzuru
Renesas Technology Corporation Wafer Process Engineering Development Department
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Inuishi Masahide
Renesas Technology Corporation Wafer Process Engineering Development Department
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Hayashi Kiyoshi
Renesas Technology Corporation Wafer Process Engineering Development Department
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Yamashita Tomohiro
Renesas Technology Corporation Wafer Process Engineering Development Department
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Hayashi Takashi
Renesas Technology Corporation Wafer Process Engineering Development Department
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Oda Hidekazu
Renesas Electronics Corporation, Hitachinaka, Ibaraki 312-8504, Japan
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Yamashita Tomohiro
Renesas Electronics Corporation, Hitachinaka, Ibaraki 312-8504, Japan
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Tsujikawa Shimpei
Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan
著作論文
- V_/E_-Driven Breakdown of Ultrathin SiON Gate Dielectrics in p-Type Metal Oxide Semiconductor Field Effect Transistors under Low-Voltage Inversion Stress
- Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond
- $V_{\text{ox}}/E_{\text{ox}}$-Driven Breakdown of Ultrathin SiON Gate Dielectrics in p-Type Metal Oxide Semiconductor Field Effect Transistors under Low-Voltage Inversion Stress