Inuishi Masahide | Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam

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概要

• 同名の論文著者
• Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itamの論文著者

関連著者

• Oda Hidekazu

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Hayashi Kiyoshi

  Renesas

• SHIGA Katsuya

  Renesas Technology Corp.

• Shiga Katsuya

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Ohji Yuzuru

  Process Technology Development Division Renesas Technology Corp.

• Hayashi Takashi

  Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam

• Yamashita Tomohiro

  Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam

• Eimori Takahisa

  Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam

• Inuishi Masahide

  Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam

• Ohji Yuzuru

  Renesas Technology Corperation, Wafer Process Engineering Development Department, 4-1 Mizuhara, Itam

• Eimori Takahisa

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Ohji Yuzuru

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Inuishi Masahide

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Hayashi Kiyoshi

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Yamashita Tomohiro

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Hayashi Takashi

  Renesas Technology Corporation Wafer Process Engineering Development Department

• Oda Hidekazu

  Renesas Electronics Corporation, Hitachinaka, Ibaraki 312-8504, Japan

• Yamashita Tomohiro

  Renesas Electronics Corporation, Hitachinaka, Ibaraki 312-8504, Japan

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著作論文

• Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond

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