Evaluation of Threshold-Voltage Variation in Silicon on Thin Buried Oxide Complementary Metal–Oxide–Semiconductor and Its Impact on Decreasing Standby Leakage Current

概要

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Threshold-voltage ($V_{\text{th}}$) variation of silicon on thin buried oxide (SOTB) complementary metal–oxide–semiconductor (CMOS) transistors and the impact of reducing the variation on leakage current were studied. Both reduction of impurity concentration in the silicon-on-insulator (SOI) layer and suppression of short-channel effect without the halo implantation were essential for reducing the $V_{\text{th}}$ variation. Using a metal-gate was also effective. The standard deviation of $V_{\text{th}}$ ($\sigma V_{\text{th}}$) for SOTB with fully silicided (FUSI) metal gate was half that for the bulk with the same gate size. This improvement can reduce the off-state leakage current summed over a large number of transistors by half in the 65-nm technology. With further scaling of the gate length, this effect can be enhanced. The SOTB of small $\sigma V_{\text{th}}$ has a strong impact on reducing leakage current in highly scaled LSI.
2009-04-25