Impact of Drain Induced Barrier Lowering on Read Scheme in Silicon Nanocrystal Memory with Two-Bit-per-Cell Operation

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概要

• 論文の詳細を見る

• The threshold voltages ($V_{\text{th}}$'s) and read schemes of silicon nanocrystal memories with two bits per cell are examined by experiments and simulations. It is found that the drain induced barrier lowering (DIBL) has a marked effect on $V_{\text{th}}$'s in the four states and thus on read schemes for detecting the four $V_{\text{th}}$'s. It is also shown that the read scheme can be selected by controlling DIBL using device parameters including gate length, injected charge fraction, and injected charge density. Suitable read schemes for low-voltage and low-power applications are discussed.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2006-02-15

著者

• Im Hyunsik

  Department Of Semiconductor Science Dongguk University

• Hiramoto Toshiro

  Institute Of Industrial Science The University Of Tokyo

• Kim Ilgweon

  Institute Of Industrial Science University Of Tokyo

• Park Sangsu

  Institute Of Industrial Science University Of Tokyo

• Im Hyunsik

  Department of Semiconductor Science, Dongguk University, 3-26 Pil-dong, Chung-gu, Seoul 100-715, Korea

• HIRAMOTO Toshiro

  Institute Industrial Science, The University of Tokyo

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