Experimental Study on the Universality of Mobility Behavior in Ultra Thin Body Metal Oxide Semiconductor Field Effect Transistors

スポンサーリンク

概要

• 論文の詳細を見る

• This paper describes the mobility behavior in ultra thin body (UTB) silicon on insulator (SOI) p-type metal oxide semiconductor field effect transistors (pMOSFETs). We propose a method of detecting scattering mechanisms in UTB pMOSFETs, and experimentally demonstrate that the mobility in an 8.1-nm-thick SOI pMOSFET degrades due only to increased acoustic phonon scattering, while other degradation mechanisms appear in a 4.5-nm-thick device. It is also demonstrated that the mobility in the 4.5-nm-thick device shows universal characteristics as a function of an effective electric field for various substrate biases, which is the same behavior as that of bulk MOSFETs.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2005-06-15

著者

• Hiramoto Toshiro

  Institute Of Industrial Science The University Of Tokyo

• Tsutsui Gen

  Institute Of Industrial Science University Of Tokyo

• Saitoh Masumi

  Institute Of Industrial Science University Of Tokyo

• Nagumo Toshiharu

  Institute Of Industrial Science The University Of Tokyo

• Hiramoto Toshiro

  Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan

• HIRAMOTO Toshiro

  Institute Industrial Science, The University of Tokyo

関連論文

• 微細MOSデバイスにおけるランダムばらつき(プロセス・デバイス・回路シミュレーション及び一般)
• 1.MOSトランジスタのスケーリングに伴う特性ばらつき(CMOSデバイスの微細化に伴う特性ばらつきの増大とその対策)
• シリコン技術
• (110)SOI基板上に作製したGAAシリコンナノワイヤの移動度評価(低電圧/低消費電力技術、新デバイス・回路とその応用)
• 「電流立上り電圧」ばらつきに起因する微細MOSトランジスタのランダム電流ばらつきの解析(低電圧/低消費電力技術,新デバイス・回路とその応用)
• DMA TEGによるSRAMのスタティックノイズマージンの直接測定と解析(低電圧/低消費電力技術,新デバイス・回路とその応用)
• 「電流立上り電圧」ばらつきに起因する微細MOSトランジスタのランダム電流ばらつきの解析(デバイス,低電圧/低消費電力技術,新デバイス・回路とその応用)
• DMA TEGによるSRAMのスタティックノイズマージンの直接測定と解析(高信頼技術,低電圧/低消費電力技術,新デバイス・回路とその応用)
• C-11-1 微細MOSトランジスタの特性ばらつきの研究(C-11.シリコン材料・デバイス,一般セッション)
• Untitled - Foreword
• Random Threshold Voltage Variability Induced by Gate-Edge Fluctuations in Nanoscale Metal-Oxide-Semiconductor Field-Effect Transistors
• Si(110)面正孔移動度における方向依存性の起源 : 極薄SOIを用いた実験的考察(IEDM特集(先端CMOSデバイス・プロセス技術))
• Room Temperature Coulomb Blockade and Low Temperature Hopping Transport in a Multiple-Dot-Channel Metal-Oxide-Semiconductor Field-Effect-Transistor ( Quantum Dot Structures)
• Fabrication of Si Nanostructures for Single Electron Device Applications by Anisotropic Etching
• Modeling of Body Factor and Subthreshold Swing in Short Channel Bulk MOSFETs
• Mobility Increase in High-Ns Region in (110)-Oriented UTB pMOSFET Through Surface Roughness Improvement
• Very Sharp Room-Temperature Negative Differential Conductance in Silicon Single-Hole Transistor with High Voltage Gain
• Temperature Dependence of Off-Current in Bulk and FD SOI MOSFETs
• High Performance Accumulated Back-Interface Dynamic Threshold SOI MOS-FET's (AB-DTMOS) with Large Body Effect at Low Supply Voltage
• (110)SOI基板上に作製したGAAシリコンナノワイヤの移動度評価(低電圧/低消費電力技術、新デバイス・回路とその応用)
• シリコンナノワイヤpMOSFET及び室温動作単正孔トランジスタにおける一軸歪みの効果(機能ナノデバイス及び関連技術)
• シリコンナノワイヤpMOSFET及び室温動作単正孔トランジスタにおける一軸歪みの効果(機能ナノデバイス及び関連技術)
• Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations(Device,Low-Power, High-Speed LSIs and Related Technologies)
• Short Channel Characteristics of Variable Body Factor FD SOI MOSFETs
• Future Electron Devices and SOI Technology : Semi-Planar SOI MOSFETs with Sufficient Body Effect
• Charge Polarity Dependence of Negative Differential Conductance in Room-Temperature Operating Silicon Single-Charge Transistors
• Evidence for Creation of Gallium Antisite Defect in Surface Region of Bleat-Treated GaAs
• Effects of Dot Size and its Distribution on Electron Number Control in Metal-Oxide-Semiconductor-Field-Effect-Transistor Memories Based on Silicon Nanocrystal Floating Dots
• Characteristic Distributions of Narrow Channel Metal-Oxide-Semiconductor Field-Effect Transistor Memories with Silicon Nanocrystal Floating Gates
• Large Threshold Voltage Shift and Narrow Threshold Voltage Distribution in Ultra Thin Body Silicon Nanocrystal Memories
• Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)
• Optimum Condutions of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs
• Optimum Conditions of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs
• Measurement of Energetic and Lateral Distribution of Interface State Density in Fully-Depleted Silicon on Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
• High-Performance Accumulated Back-Interface Dynamic Threshold SOI MOSFET (AB-DTMOS) with Large Body Effect at Low Supply Voltage
• Measurement of Energetic and Lateral Distribution of Interface State Density in FD SOI MOSFETs
• Suppression of Geometric Component of Charge Pumping Current in Thin Film Silicon on Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
• Characteristics of Narrow Channel MOSFET Memory Based on Silicon Nanocrystals
• Effects of Interface Traps on Charge Retention Characteristics in Silicon-Quantum-Dot-Based Metal-Oxide-Semiconductor Diodes
• Characteristics of Narrow Channel MOSFET Memory Based on Silicon Nanocrystals
• Extremely Large Amplitude of Random Telegraph Signals in a Very Narrow Split-Gate MOSFET at Low Temperatures
• Re-Examination of Impact of Intrinsic Dopant Fluctuations on Static RAM (SRAM) Static Noise Margin
• Origin of Critical Substrate Bias in Variable Threshold Voltage Complementary MOS (VTCMOS)
• Origin of Critical Substrate Bias in Variable Threshold Voltage CMOS
• Special Issue on Advanced Sub-0.1 μm CMOS Devices
• Mobility Degradation in (110)-Oriented Ultra-thin Body Double-Gate pMOSFETs with SOI Thickness of less than 5nm
• Large Coulomb-Blockade Oscillations and Negative Differential Conductance in Silicon Single-Electron Transistors with [100]- and [110]-Directed Channels at Room Temperature
• Room Temperature Demonstration of Variable Full Width at Half Maximum of Coulomb Oscillation in Silicon Single-Hole Transistor
• Reverse Short-Channel Effect of Body Factor in Low-Fin Field-Effect Transistors Induced by Corner Effect
• Effects of Discrete Quantum Levels on Electron Transport in Silicon Single-Electron Transistors with an Ultra-Small Quantum Dot
• Re-examination of Impact of Intrinsic Dopant Fluctuations on SRAM Static Noise Margin
• Impact of Drain Induced Barrier Lowering on Read Scheme in Silicon Nanocrystal Memory with Two-Bit-per-Cell Operation
• Suppression of Stand-by Tunnel Current in Ultra-Thin Gate Oxide MOSFETs by Dual Oxide Thickness MTCMOS(DOT-MTCMOS)
• Large Temperature Dependence of Coulomb Blockade Oscillations in Room-Temperature Operating Silicon Single-Hole Transistor
• Room-Temperature Operation of Current Switching Circuit Using Integrated Silicon Single-Hole Transistors
• Room-Temperature Demonstration of Low-Voltage Static Memory Based on Negative Differential Conductance in Silicon Single-Hole Transistors
• Origin of Larger Drain Current Variability in N-Type Field-Effect Transistors Analyzed by Variability Decomposition Method
• Fabrication of Nano-Scale Point Contact Metal-Oxide-Semiconductor Field-Effect-Transistors Using Micrometer-Scale Design Rule
• DMA SRAM TEGにより解析したSRAMのスタティックノイズマージンにおけるDIBLばらつきの影響(IEDM特集(先端CMOSデバイス・プロセス技術))
• Modeling of Body Factor and Subthreshold Swing in Bulk Metal Oxide Semiconductor Field Effect Transistors in Short-Channel Regime
• Impact of Oxide Thickness Fluctuation and Local Gate Depletion on Threshold Voltage Variation in Metal–Oxide–Semiconductor Field-Effect Transistors
• Consideration of Random Dopant Fluctuation Models for Accurate Prediction of Threshold Voltage Variation of Metal–Oxide–Semiconductor Field-Effect Transistors in 45 nm Technology and Beyond
• 微細MOSトランジスタにおけるDIBLおよび電流立上り電圧ばらつきの統計解析(低電圧/低消費電力技術,新デバイス・回路とその応用)
• Takeuchiプロットを用いたHigh-k/Metal-Gate MOSFETのばらつき評価(低電圧/低消費電力技術,新デバイス・回路とその応用)
• 微細MOSトランジスタにおけるDIBLおよび電流立上り電圧ばらつきの統計解析(低電圧/低消費電力技術,新デバイス・回路とその応用)
• Takeuchiプロットを用いたHigh-k/Metal-Gate MOSFETのばらつき評価(低電圧/低消費電力技術,新デバイス・回路とその応用)
• 完全空乏型SOI MOSFETにおける特性ばらつきとランダムテレグラフノイズ(プロセス科学と新プロセス技術)
• Evaluation of Threshold-Voltage Variation in Silicon on Thin Buried Oxide Complementary Metal–Oxide–Semiconductor and Its Impact on Decreasing Standby Leakage Current
• Wide-Range Threshold Voltage Controllable Silicon on Thin Buried Oxide Integrated with Bulk Complementary Metal Oxide Semiconductor Featuring Fully Silicided NiSi Gate Electrode
• Experimental Study on Mobility Universality in (100) Ultrathin Body nMOSFETs with SOI Thickness of 5 nm
• Suppression of Within-Device Variability in Intrinsic Channel Tri-Gate Silicon Nanowire Metal-Oxide-Semiconductor Field-Effect Transistors (Special Issue : Solid State Devices and Materials (1))
• Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors
• Large Temperature Dependence of Coulomb Blockade Oscillations in Room-Temperature-Operating Silicon Single-Hole Transistor
• Room-Temperature Operation of Current Switching Circuit Using Integrated Silicon Single-Hole Transistors
• 100億トランジスタのしきい値電圧ばらつき(IEDM特集(先端CMOSデバイス・プロセス技術))
• Temperature Dependence of Off-Current in Bulk and Fully Depleted SOI MOSFETs
• On the Origin of Negative Differential Conductance in Ultranarrow-Wire-Channel Silicon Single-Electron and Single-Hole Transistors
• Superior $\langle 110\rangle$-Directed Electron Mobility to $\langle 100\rangle$-Directed Electron Mobility in Ultrathin Body (110) n-Type Metal–Oxide–Semiconductor Field-Effect Transistors
• Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)
• Impact of Drain Induced Barrier Lowering on Read Scheme in Silicon Nanocrystal Memory with Two-Bit-per-Cell Operation
• Room-Temperature Observation of Negative Differential Conductance Due to Large Quantum Level Spacing in Silicon Single-Electron Transistor
• Variable Body Effect Factor Fully Depleted Silicon-On-Insulator Metal Oxide Semiconductor Field Effect Transistor for Ultra Low-Power Variable-Threshold-Voltage Complementary Metal Oxide Semiconductor Applications
• Electron Mobility in Silicon Gate-All-Around [100]- and [110]-Directed Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor on (100)-Oriented Silicon-on-Insulator Substrate Extracted by Improved Split Capacitance–Voltage Method
• Extremely Large Amplitude Random Telegraph Signals in a Very Narrow Split-Gate MOSFET at Low Temperatures
• Experimental Study on the Universality of Mobility Behavior in Ultra Thin Body Metal Oxide Semiconductor Field Effect Transistors
• Experimental Study on Mobility in (110)-Oriented Ultrathin-Body Silicon-on-Insulator n-Type Metal Oxide Semiconductor Field-Effect Transistor with Single- and Double-Gate Operations
• Current Drive Improvement Using Enhanced Body Effect Factor Due to Finite Inversion Layer Thickness in Variable-Threshold-Voltage Complementary MOS (VTCMOS)
• Optimum Device Consideration for Standby Power Reduction Scheme Using Drain-Induced Barrier Lowering
• Statistical Analysis of Subthreshold Swing in Fully Depleted Silicon-on-Thin-Buried-Oxide and Bulk Metal--Oxide--Semiconductor Field Effect Transistors
• Integration of Complementary Metal--Oxide--Semiconductor 1-Bit Analog Selectors and Single-Electron Transistors Operating at Room Temperature
• Reverse Short-Channel Effect of Body Factor in Low-Fin Field-Effect Transistors Induced by Corner Effect
• Silicon Single-Hole Transistor with Large Coulomb Blockade Oscillations and High Voltage Gain at Room Temperature
• Effects of Side Surface Roughness on Carrier Mobility in Tri-Gate Single Silicon Nanowire Metal--Oxide--Semiconductor Field-Effect Transistors
• Direct Measurement of Carrier Mobility in Intrinsic Channel Tri-Gate Single Silicon Nanowire Metal--Oxide--Semiconductor Field-Effect Transistors
• Mobility Degradation in (110)-Oriented Ultrathin-Body Double-Gate p-Type Metal–Oxide–Semiconductor Field-Effect Transistors with Silicon-on-Insulator Thickness of Less than 5 nm
• Short-Channel Characteristics of Variable-Body-Factor Fully-Depleted Silicon-On-Insulator Metal–Oxide–Semiconductor-Field-Effect-Transistors
• Large Electron Addition Energy above 250 meV in a Silicon Quantum Dot in a Single-Electron Transistor
• Statistical Analysis of Current Onset Voltage (COV) Distribution of Scaled MOSFETs
• NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM
• 超低電力LSIを実現する薄膜BOX-SOI(SOTB)CMOS技術(SOIテクノロジ,低電圧/低消費電力技術,新デバイス・回路とその応用)

もっと見る 閉じる

スポンサーリンク