Transient Capacitance in Metal-Oxide-Semiconductor Structures with Stacked Gate Dielectrics
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概要
- 論文の詳細を見る
Changes in transient capacitances during application of step voltages to the gate electrode of metal-oxide-semiconductor (MOS) structures with stacked gate dielectrics were investigated. The behaviors of the changes in transient capacitance varied depending on the thickness of high dielectric films. The results indicate that negative charges were trapped near the gate electrodes during stress voltage application, while positive charges were trapped near the Si/SiO2 interface. These charges in gate films were released at different time constants during relaxation.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2004-11-15
著者
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Torii Kazuyoshi
Semiconductor Leading Edge Technologies Inc.
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HIGUCHI Keiichi
Institute of Applied Physics, University of Tsukuba
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Hasunuma Ryu
Institute Of Applied Physics University Of Tsukuba
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Yamabe Kikuo
Institute Of Applied Physics University Of Tsukuba
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Goto Masakazu
Institute Of Applied Physics University Of Tsukuba
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Goto Masakazu
Institute of Applied Physics, University of Tsukuba, Tsukuba, Ibaraki 305-8573, Japan
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