Improvement of Dielectric Properties on Deposited SiO2 Caused by Stress Relaxation with Thermal Annealing
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概要
- 論文の詳細を見る
The relationship between the electrical and structural characteristics of tetraethylorthosilicate (TEOS) SiO2 has been investigated to reveal the mechanism of the improvement of the dielectric properties with thermal annealing. Stress relaxation in TEOS–SiO2 caused by thermal annealing was observed as a blue shift of the infrared absorption spectral peak in a Fourier transform infrared attenuated total reflection (FTIR-ATR) spectrum. It was concluded that the stress relaxation increased the band gap of TEOS–SiO2, resulting in suppression of the leakage current. Additionally, thermal desorption spectroscopy (TDS) performed to investigate the phenomena of film densification by thermal annealing.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2009-05-25
著者
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Hasunuma Ryu
Institute Of Applied Physics University Of Tsukuba
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Yamabe Kikuo
Institute Of Applied Physics University Of Tsukuba
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Hasunuma Ryu
Institute of Applied Physics, University of Tsukuba, Tsukuba, Ibaraki 305-8573, Japan
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Sometani Mitsuru
Institute of Applied Physics, University of Tsukuba, Tsukuba, Ibaraki 305-8573, Japan
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Ogino Masaaki
Semiconductor Process R&D Section, Semiconductor Process R&D Department, Electron Device Laboratory, Fuji Electric Device Technology Co., Ltd., 4-15-1, Matsumoto, Nagano 390-0821, Japan
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Kuribayashi Hitoshi
Semiconductor Process R&D Section, Semiconductor Process R&D Department, Electron Device Laboratory, Fuji Electric Device Technology Co., Ltd., 4-15-1, Matsumoto, Nagano 390-0821, Japan
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Sugahara Yoshiyuki
Semiconductor Process R&D Section, Semiconductor Process R&D Department, Electron Device Laboratory, Fuji Electric Device Technology Co., Ltd., 4-15-1, Matsumoto, Nagano 390-0821, Japan
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Ogino Masaaki
Semiconductor Process R&D Section, Semiconductor Process R&D Department, Electron Device Laboratory, Fuji Electric Device Technology Co., Ltd., 4-15-1, Matsumoto, Nagano 390-0821, Japan
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Kuribayashi Hitoshi
Semiconductor Process R&D Section, Semiconductor Process R&D Department, Electron Device Laboratory, Fuji Electric Device Technology Co., Ltd., 4-15-1, Matsumoto, Nagano 390-0821, Japan
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Sugahara Yoshiyuki
Semiconductor Process R&D Section, Semiconductor Process R&D Department, Electron Device Laboratory, Fuji Electric Device Technology Co., Ltd., 4-15-1, Matsumoto, Nagano 390-0821, Japan
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