High-Speed and Low-Power n^+-p^+ Double-Gate SOI CMOS
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概要
- 論文の詳細を見る
We propose and fabricate n^+-p^+ double-gate SOI MOSFETs for which threshold voltage is controlled by interaction between the two gates. Devices have excellent short channel immunity, despite a low channel doping concentration of 10^lt15gt cm^lt-3gt, and enable us to design a threshold voltage below 0.3 V while maintaining an almost ideal subthreshold swing. We demonstrated 27 ps CMOS inverter delay with a gate length of 0.19μm, which is, to our knowledge, the lowest delay for this gate length despite rather a thick 9 nm gate oxide. This high performance is a result of the low threshold voltage and negligible drain capacitance. We also showed theoretically that we can design a 0.1μm gate length device with an ideal subthreshold swing, and that we can expect less than 10 ps inverter delay at a supply voltage of 1 V.
- 社団法人電子情報通信学会の論文
- 1995-04-25
著者
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Horie H
Fujitsu Lab. Ltd. Atsugi Jpn
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TOSAKA Yoshiharu
Fujitsu Laboratories Ltd.
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SUZUKI Kunihiro
Fujitsu Laboratories Ltd.
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Suzuki Kunihiro
Department Of Histology Cytology And Developmental Anatomy Nihon University School Of Dentistry At M
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Suzuki K
Oki Electric Ind. Co. Ltd. Hachioji‐shi Jpn
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SUGII Toshihiro
FUJITSU LABORATORIES LTD.
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Tanaka Tsuyoshi
Semiconductor Device Research Center Semiconductor Company Matsushita Electric Industrial Co. Ltd.
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Terahara Takafumi
The Authors Are With Optoelectronic Systems Laboratory Network System Laboratories Fujitsu Laborator
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Tanaka T
Semiconductor Device Research Center Semiconductor Company Matsushita Electric Industrial Co. Ltd.
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HORIE Hiroshi
Fujitsu Laboratories Ltd.
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TANAKA Tetsu
Fujitsu Laboratories Ltd.
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Sugii T
Fujitsr Ltd. Akiruno-shi Jpn
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Suzuki Kunihiro
Fujitsu Laboratories Limited., 10-1 Morinosato-Wakamiya, Atsugi 243-0197, Japan
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