Fabrication and Delay Time Analysis of Deep Submicron CMOS Devices

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This paper describes the fabrication of 0.1μm gate length CMOS devices and analysis of delay time by circuit simulation. In order to reduce the gate resistance, TiN capped cobalt salicide technology is applied to the fabrication of 0.1μm CMOS devices. Gate sheet resistance with a 0.1μm gate is as low as 5 Ω/sq. Propagation delay times of 0.1μm and 0.15μm CMOS inverter are 21 ps and 36 ps. Simulated propagation delay time agreed fairly well with experimental results. For gate length over 0.15μm, intrinsic delay in CMOS devices is the main delay factor. This suggests that increasing current drivability is the most efficient way to improve propagation delay time. At 0.1μm, each parasitic component and intrinsic delay have similar contributions on device speed due to the short channel effect. To improve delay time, we used rapid thermal annealing or a high dose LDD structure. With this structure, drain current increases by more than 1.3 times and simulation predicted a delay time of 28 ps is possible with 0.15μm CMOS inverters.
社団法人電子情報通信学会の論文
1995-03-25