A New SOI-Lateral Bipolar Transistor for High-Speed Operation
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概要
- 論文の詳細を見る
We proposed a new SOI-lateral bipolar transistor. The device is featured by a thin base (simulated thickness was 80 nm) and base contact which was formed just on an intrinsic base. The device has sufficient junction breakdown voltage, but a current gain of 10, due to the degraded forward-biased emitter-base junction characteristic. The current gain was improved to 30 by keeping the base region about 2 μm from the highly arsenic-implanted emitter. The device structure seems to be ideal for a future high-speed bipolar transistor.
- 社団法人応用物理学会の論文
- 1991-12-15
著者
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Kojima Miki
Eda Application Engineering Worldwide Development Application Specific Products Tsukuba Technology C
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SUGII Toshihiro
FUJITSU LABORATORIES LTD.
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ARIMOTO Yoshihiro
Fujitsu Laboratories Ltd.
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Fukano Tetsu
FUJITSU LABORATORIES LTD.
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KOJIMA Manabu
Fujitsu Laboratories Ltd.
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Sugii T
Fujitsr Ltd. Akiruno-shi Jpn
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ARIMOTO Yoshihiro
System LSI Development Labs., FUJITSU LABORATORIES LTD.
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Fukuroda Atsushi
FUJITSU LABORATORIES LTD.
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Arimoto Y
System Lsi Development Labs. Fujitsu Laboratories Ltd.
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