Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide
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概要
- 論文の詳細を見る
We studied the diffusion of impurities in dual polysilicon gates, and found that this phenomenon can effectively be treated as diffusion from a constant concentration diffusion source for both p+ and n+ polysilicon gates. We derived a model for the critical time required to obtain a flat profile. We then clarified the thermal budget required for suppressing gate depletion and impurity penetration through a gate oxide. According to our study, the thermal budget for n-type metal-oxide-semiconductor-field-effect-transistor (MOSFET) is always wider than that for p-type MOSFET, and the budget for p-type MOSFET is wide enough for realizing a flat profile without impurity penetration using pure SiO2 if B is available instead of BF2.
- INSTITUTE OF PURE AND APPLIED PHYSICSの論文
- 1996-02-28
著者
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KATAOKA Yuji
Fujitsu Laboratories Ltd.
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SUZUKI Kunihiro
Fujitsu Laboratories Ltd.
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AOYAMA Takayuki
Fujitsu Laboratories Lid.
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TADA Yoko
Fujitsu Laboratories Ltd.
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SATOH Akira
FUJITSU LABORATORIES LTD.
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SUGII Toshihiro
FUJITSU LABORATORIES LTD.
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NAMURA Itaru
Fujitsu Laboratories Ltd.
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INOUE Fumihiko
Fujitsu Laboratories Ltd.
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Aoyama Takayuki
Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-01, Japan
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Kataoka Yuji
Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-01, Japan
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Inoue Fumihiko
Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-01, Japan
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Suzuki Kunihiro
Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-01, Japan
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Suzuki Kunihiro
Fujitsu Laboratories Limited., 10-1 Morinosato-Wakamiya, Atsugi 243-0197, Japan
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