Potential of and Issues with Multiple-Stressor Technology in High-Performance 45 nm Generation Devices

スポンサーリンク

概要

• 論文の詳細を見る

• In this paper, we describe multiple-stressor technology (MST) for high-performance 45-nm-node devices. The combination of two or more stressors, namely, polygate stressor (PGS)/tensile stress liner (SL) for n-channel field-effect transistor (NFET), and embedded SiGe/compressive SL for p-channel field-effect transistor (PFET), is integrated into complementary metal–oxide–semiconductor (CMOS) process and its potential for device performance enhancement is investigated. Moreover, the issues of MST are also discussed from the viewpoint of variations in device characteristics under an extremely high channel strain, which are not pronounced in the previous technology with its relatively low strains.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2007-04-30

著者

• AOYAMA Takayuki

  Fujitsu Laboratories Lid.

• Miyashita Toshihiko

  Fujitsu Laboratories Ltd.

• Satoh Shigeo

  Fujitsu Laboratories Ltd.

• Tamura Naoyoshi

  Fujitsu Lab. Ltd.

• Aoyama Takayuki

  Fujitsu Laboratories Ltd., 50 Fuchigami, Akiruno, Tokyo 193-0197, Japan

• Satoh Shigeo

  Fujitsu Laboratories Ltd., 50 Fuchigami, Akiruno, Tokyo 193-0197, Japan

• Hatada Akiyoshi

  Fujitsu Microelectonics, Ltd., 1500 Mizono, Tado, Kuwana, Mie 511-0192, Japan

• Owada Tamotsu

  Fujitsu Ltd., 50 Fuchigami, Akiruno, Tokyo 193-0197, Japan

• Shimamune Yousuke

  Fujitsu Laboratories Ltd., 50 Fuchigami, Akiruno, Tokyo 193-0197, Japan

• Hatada Akiyoshi

  Fujitsu Laboratories Ltd., 50 Fuchigami, Akiruno, Tokyo 193-0197, Japan

関連論文

• Silicon-Hydrogen Bonds in Silicon Native Oxides Formed during Wet Chemical Treatments
• Investigation of Degradation model for Ultra-thin Gate Dielectrics
• Suppression of Transient Enhanced Diffusion by Local-Oxidation-Silicon-Induced Stress
• Suppression of Transient Enhanced Diffusion by LOCOS Induced Stress
• Analysis and modeling of size dependent mobility enhancement due to mechanical stress
• High Tilt Angle Ion Implantation into Polycrystalline Si Gates
• Analysis of Non-Uniform Boron Penetration of Nitrided Oxide in PMOSFETs Considering Two-Dimensional Nitrogen Distribution
• Boron Penetration Enhanced by Gate Ion Implantation Damage in PMOSFETs
• Hydrogen-Enhanced Boron Penetration in PMOS Devices during SiO_2 Chemical Vapor Deposition
• Hydrogen-Enhancing Boron Penetration in P-MOS Devices during SiO_2 Chemical Vapor Deposition
• Boron Diffusion in Nitrided-Oxide Gate Dielectrics Leading to High Suppression of Boron Penetration in P-MOSFETs
• Boron Diffusion in Nitrided Oxide Gate Dielectrics Leading to High Suppression of Boron Penetration in P-MOSFETs
• Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide
• Thermal Budget for Fabricating A Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide
• Electrical Properties of SiN/HfO_2/SiON Gate Stacks with High Thermal Stability(High-κ Gate Dielectrics)
• Dopant Profile Design Methodology for 65nm Generation via Inverse Modeling
• Study of L_ dependence of 2-D carrier profile in N-FET by Scanning Tunneling Microscopy
• Boron Diffusion in SiO_2 Involving High-Concentration Effects
• Boron Diffusion in SiO_2 Involving High-Concentration Effects
• Scanning Tunneling Microscopy Study of Submicron-Sized pn Junction on Si(001) Surfaces
• Scaling Trends and Mitigation Techniques for Soft Errors in Flip-Flops
• Scaling Law for Secondary Cosmic-Ray Neutron-Induced Soft-Errors in DRAMs
• Impact of Current Gain Increment Effect on Alpha Particle Induced Soft Errors in SOI DRAMs
• Theoretical Study of Alpha-Particle-Induced Soft Errors in Submicron SOI SRAM (Special Issue on ULSI Memory Technology)
• Novel Soft Error Hardened Latches and Flip-Flops
• Neutron-induced Soft-Error Simulation Technology for Logic Circuits
• Direct measurement of the offset spacer effect on the carrier profiles in sub-50nm p-MOSFETs
• Design and Optimization of Gate Sidewall Spacers to Achieve 45 nm Ground Rule for High-Performance Applications
• Advanced Input/Output Technology Using Laterally Modulated Channel Metal–Oxide–Semiconductor Field Effect Transistor for 65-nm Node System on a Chip
• Effect of Implanted Oxygen and Nitrogen on Mobility and Generation of Dislocation in SiGe/Si Heterostructure
• Extraction of Depth-Dependent Lateral Standard Deviation from One-Dimensional Tilted Implantation Profiles
• Analytical Models for Symmetric Thin-Film Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistors
• Sub-2nm Equivalent SiO_2 Thickness Ta_2O_5 for Gate Dielectric Using RTA+UV/O_3
• Soft Error Hardened Latch and Its Estimation Method
• Neutron-Induced Soft-Error Simulation Technology for Logic Circuits
• Technological Trends of Soft Error Estimation Based on Accurate Estimation Method
• Threshold Voltage Instability of 45-nm-node Poly-Si-or FUSI-Gated SRAM Transistors Caused by Dopant Lateral Diffusion in Poly-Si
• Impact of Metal Gate/High-k Interface in Mo Metal Gated MOSFETs with HfO_2 Gate Dielectrics
• Process Integration Issues on Mo-Metal-Gated MOSFETs with HfO2 High-k Gate Dielectrics
• Mechanical Stress Evaluation of Si Metal--Oxide--Semiconductor Field-Effect Transistor Structure Using Polarized Ultraviolet Raman Spectroscopy Measurements and Calibrated Technology-Computer-Aided-Design Simulations
• Observation of Dislocation Motion in Si1-xGex Thin Film on Si Substrate by Laser Scattering Method
• High Tilt Angle Ion Implantation into Polycrystalline Si Gates
• Study of Gate Length Dependence of Two-dimensional Carrier Profile in N-FET by Scanning Tunneling Microscopy
• Study of Peeling at Doped NiSi/SiO2 Interface
• Potential of and Issues with Multiple-Stressor Technology in High-Performance 45 nm Generation Devices
• Direct Measurement of Offset Spacer Effect on Carrier Profiles in Sub-50 nm p-Metal Oxide Semiconductor Field-Effect Transistors
• Impact of Parasitic Bipolar Effect on Single-Event Upset in p-Type Metal--Oxide--Semiconductor Field Effect Transistor with Embedded SiGe
• Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide
• Effect of Ion Implantation on Dislocation Motion in SiGe/Si Heterostructure

もっと見る 閉じる

スポンサーリンク