Sub-2nm Equivalent SiO_2 Thickness Ta_2O_5 for Gate Dielectric Using RTA+UV/O_3

スポンサーリンク

概要

論文の詳細を見る
2000-08-28

著者

関連論文

Silicon-Hydrogen Bonds in Silicon Native Oxides Formed during Wet Chemical Treatments
Suppression of Transient Enhanced Diffusion by Local-Oxidation-Silicon-Induced Stress
Suppression of Transient Enhanced Diffusion by LOCOS Induced Stress
High Tilt Angle Ion Implantation into Polycrystalline Si Gates
Analysis of Non-Uniform Boron Penetration of Nitrided Oxide in PMOSFETs Considering Two-Dimensional Nitrogen Distribution
Boron Penetration Enhanced by Gate Ion Implantation Damage in PMOSFETs
Hydrogen-Enhanced Boron Penetration in PMOS Devices during SiO_2 Chemical Vapor Deposition
Hydrogen-Enhancing Boron Penetration in P-MOS Devices during SiO_2 Chemical Vapor Deposition
Boron Diffusion in Nitrided-Oxide Gate Dielectrics Leading to High Suppression of Boron Penetration in P-MOSFETs
Boron Diffusion in Nitrided Oxide Gate Dielectrics Leading to High Suppression of Boron Penetration in P-MOSFETs
Sb Multiple Ion Implanted Channel for Low V_, Deep Submicron SOI-pMOSFETs
Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide
Vth Rolloff Free Sub 0.1μm SOI MOSFETs Using Counter Doping into a Uniformly and Heavily Doped Channel Region
Thermal Budget for Fabricating A Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide
Fabrication and Delay Time Analysis of Deep Submicron CMOS Devices
Ti Salicide Process for Subquarter-Micron CMOS Devices (Special Issue on Quarter Micron Si Device and Process Technologies)
Electrical Properties of SiN/HfO_2/SiON Gate Stacks with High Thermal Stability(High-κ Gate Dielectrics)
Dopant Profile Design Methodology for 65nm Generation via Inverse Modeling
Scenario of Source/Drain Extension and Halo Engineering for High Performance 50nm SOI-pMOSFET
High-Speed and Low-Power n^+-p^+ Double-Gate SOI CMOS
Study of L_ dependence of 2-D carrier profile in N-FET by Scanning Tunneling Microscopy
Boron Diffusion in SiO_2 Involving High-Concentration Effects
Boron Diffusion in SiO_2 Involving High-Concentration Effects
Scanning Tunneling Microscopy Study of Submicron-Sized pn Junction on Si(001) Surfaces
Theoretical Study of Alpha-Particle-Induced Soft Errors in Submicron SOI SRAM (Special Issue on ULSI Memory Technology)
Direct measurement of the offset spacer effect on the carrier profiles in sub-50nm p-MOSFETs
Advanced Input/Output Technology Using Laterally Modulated Channel Metal–Oxide–Semiconductor Field Effect Transistor for 65-nm Node System on a Chip
High-Speed SOI Bipolar Transistors Using Bonding and Thinning Techniques
High Frequency Characteristics of Dynamic Threshold-Voltage MOSFET (DTMOS) under Ultra-Low Supply Voltage (Special Issue on Ultra-High-Speed IC and LSI Technology)
A New SOI-Lateral Bipolar Transistor for High-Speed Operation
Achieving High Current Gain and Low Emitter Resistance with the SiC_x:F Widegap Emitter
Sub-2nm Equivalent SiO_2 Thickness Ta_2O_5 for Gate Dielectric Using RTA+UV/O_3
Impact Ionization in 0.1 μm Metal-Oxide-Semiconductor Field-Effect Transistors
Current Status and Forecast in High-Performance CMOS Device Technology
Oxynitride Pad LOCOS (ON-LOCOS) Isolation Technology for Gigabit DRAMs
New Method of Extracting Inversion Layer Thickness and Charge Profile and Its Impact on Scaled MOSFETs
Threshold Voltage Instability of 45-nm-node Poly-Si-or FUSI-Gated SRAM Transistors Caused by Dopant Lateral Diffusion in Poly-Si
Impact of Metal Gate/High-k Interface in Mo Metal Gated MOSFETs with HfO_2 Gate Dielectrics
Report on the 2001 Symposium on VLSI Technology
Process Integration Issues on Mo-Metal-Gated MOSFETs with HfO2 High-k Gate Dielectrics
Si Wafer Bonding with Ta Silicide Formation
High Tilt Angle Ion Implantation into Polycrystalline Si Gates
Study of Gate Length Dependence of Two-dimensional Carrier Profile in N-FET by Scanning Tunneling Microscopy
Study of Peeling at Doped NiSi/SiO2 Interface
Potential of and Issues with Multiple-Stressor Technology in High-Performance 45 nm Generation Devices
Direct Measurement of Offset Spacer Effect on Carrier Profiles in Sub-50 nm p-Metal Oxide Semiconductor Field-Effect Transistors
Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide

もっと見る

スポンサーリンク