Suppression of Transient Enhanced Diffusion by Local-Oxidation-Silicon-Induced Stress

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概要

• 論文の詳細を見る
• 1999-04-30

著者

• AOYAMA Takahiro

  Daihen Co.

• Aoyama T

  Hitachi Ltd. Ibaraki Jpn

• AOYAMA Takayuki

  Fujitsu Laboratories Lid.

• ARIMOTO Hiroshi

  Fujitsu Laboratories Ltd.

• HORIUCHI Kei

  Fujitsu Laboratories Ltd.

• NAKAMURA Satoshi

  Fujitsu Laboratories Ltd.

• ARIMOTO Hiroshi

  Semiconductor Leading Edge Technologies

• Horiuchi K

  Fujitsu Laboratories Ltd.

• Horiuchi Kei

  Fujitsu Laboratories

• OKUNO Masaki

  Fujitsu Laboratories Limited

• Arimoto H

  Semiconductor Leading Edge Technologies Inc.

• Arimoto Hiroshi

  Fujitsu Laboratories Limited

• Nakamura S

  Fujitsu Laboratories Limited

• Nakamura Satoshi

  Fujitsu Laboratories Limited

関連論文

• In Situ Formation of Ohmic Contact Electrodes of Cu and Ag onto the Fractured Surface of (Bi, Pb)-Sr-Ca-Cu-O Ceramics
• Silicon-Hydrogen Bonds in Silicon Native Oxides Formed during Wet Chemical Treatments
• Suppression of Transient Enhanced Diffusion by Local-Oxidation-Silicon-Induced Stress
• Suppression of Transient Enhanced Diffusion by LOCOS Induced Stress
• Ru Electrode Deposited by Sputtering in Ar/O_2 Mixture Ambient
• Interfacial Layers between Si and Ru Films Deposited by Sputtering in Ar/O_2 Mixture Ambient
• High Tilt Angle Ion Implantation into Polycrystalline Si Gates
• Analysis of Non-Uniform Boron Penetration of Nitrided Oxide in PMOSFETs Considering Two-Dimensional Nitrogen Distribution
• Boron Penetration Enhanced by Gate Ion Implantation Damage in PMOSFETs
• Hydrogen-Enhanced Boron Penetration in PMOS Devices during SiO_2 Chemical Vapor Deposition
• Hydrogen-Enhancing Boron Penetration in P-MOS Devices during SiO_2 Chemical Vapor Deposition
• Boron Diffusion in Nitrided-Oxide Gate Dielectrics Leading to High Suppression of Boron Penetration in P-MOSFETs
• Boron Diffusion in Nitrided Oxide Gate Dielectrics Leading to High Suppression of Boron Penetration in P-MOSFETs
• Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide
• Thermal Budget for Fabricating A Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide
• Sub-100-nm Device Fabrication using Proximity X-Ray Lithography at Five Levels
• Patterning Yield of Sub-100-nm Holes Limited by Fluctuation of Exposure and Development Reactions in Synchrotron Radiation Lithography Using Biased Mask Patterns
• Lithographic Performance of a Chemically Amplified Resist Developed for Synchrotron Radiation Lithography in the Sub-100-nm Region
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• High-Speed Proximity Effect Correction System for Electron-Beam Projection Lithography by Cluster Processing
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• Evaluation of Performance of Proximity Effect Correction in Electron Projection Lithography
• Three-Dimensional Proximity Effect Correction for Multilayer Structures in Electron Beam Lithography
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• Application of Electron Projection Lithography to Via Formation in Two-Layer Metallization
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• Study of L_ dependence of 2-D carrier profile in N-FET by Scanning Tunneling Microscopy
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• Evaluation of Photoemitted Current from SiO_2 Film on Silicon During Synchrotron Radiation Irradiation
• Synchrotron Radiation-Assisted Silicon Film Growth by Irradiation Parallel to the Substrate
• Numerical Study of Effect of Fabrication Damage on Carrier Dynamics in MQW Narrow Wires
• Leakage Current Reduction of Poly-Si Thin Film Transistors by Two-Step Annealing
• KrF Resist Pattern Monitoring by Ellipsometry
• 100-keV Focused Ion Beam System for Field Ion Source : Lithography Technology
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• Evaluation of LOCOS Induced Stress Using Raman Spectroscopy with an Al-Mask
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• TEM Observations of Initial Crystallization States for LPCVD Si Films : Condensed Matter
• Fabrication of Sub-100 nm Wires and Dots in GaAs/AlGaAs Multiquantum Well Using Focused Ion Beam Lithography
• Evaluation of Shot Position Error in Electron Beam Lithography Using Overlay Metrology with 'One-Shot' Inspection Mark
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• Precise Line-and-Space Monitoring Results by Ellipsometry
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• Three-Dimensional Proximity Effect Correction for Multilayer Structures in Electron Beam Lithography
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• Process Integration Issues on Mo-Metal-Gated MOSFETs with HfO2 High-k Gate Dielectrics
• Improved Electron Mobility of Two-Dimensional Electron Gas Formed Area-Selectively in GaAs/AlGaAs Heterostructure by Focused Si Ion Beam Implantation and MBE Overgrowth
• Application of Electron Projection Lithography to Via Formation in Two-Layer Metallization
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• Study of Gate Length Dependence of Two-dimensional Carrier Profile in N-FET by Scanning Tunneling Microscopy
• Study of Peeling at Doped NiSi/SiO2 Interface
• High-Speed Proximity Effect Correction System for Electron-Beam Projection Lithography by Cluster Processing
• Full-Chip Lithography Verification for Multilayer Structure in Electron-Beam Lithography
• Potential of and Issues with Multiple-Stressor Technology in High-Performance 45 nm Generation Devices
• Highly Accurate Proximity Effect Correction for 100 kV Electron Projection Lithography
• Direct Measurement of Offset Spacer Effect on Carrier Profiles in Sub-50 nm p-Metal Oxide Semiconductor Field-Effect Transistors
• Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide
• The Contact Resistance of the YBa2Cu3O7-δ-Metal Film System

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