Sub-100-nm Device Fabrication using Proximity X-Ray Lithography at Five Levels

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We applied proximity X-ray lithography at five levels (mark, isolation, gate, contact and wiring) to fabricate devices at a scale of 100 nm and lower. Low-contrast masks and chemically amplified resists were used, and a critical dimension (CD) variation (3$\sigma$) within 10% of the pattern width at a scale of 100 nm was obtained at each layer. The resolution remained good down to 80 nm isolation gates at a gap of 15 $\mu$m. Overlay accuracy ($\text{mean}\pm 3\sigma$) at each layer was within 40 nm, especially at the contact-hole layer which was below 25 nm. We evaluated the fabricated device performance for subthreshold characteristics, hot-carrier reliability and threshold voltage fluctuations. Good characteristics were obtained for n-channel metal oxide semiconductor field effect transistor (n-MOSFET) devices that scale into the 100 nm regime. In this paper, we demonstrate the feasibility of X-ray lithography in process for 100-nm-and-lower devices.
2000-12-30