Report on the 2001 Symposium on VLSI Technology
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概要
- 論文の詳細を見る
- 2002-01-10
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関連論文
- Sb Multiple Ion Implanted Channel for Low V_, Deep Submicron SOI-pMOSFETs
- Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide
- Vth Rolloff Free Sub 0.1μm SOI MOSFETs Using Counter Doping into a Uniformly and Heavily Doped Channel Region
- Thermal Budget for Fabricating A Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide
- Fabrication and Delay Time Analysis of Deep Submicron CMOS Devices
- Ti Salicide Process for Subquarter-Micron CMOS Devices (Special Issue on Quarter Micron Si Device and Process Technologies)
- Electrical Properties of SiN/HfO_2/SiON Gate Stacks with High Thermal Stability(High-κ Gate Dielectrics)
- Dopant Profile Design Methodology for 65nm Generation via Inverse Modeling
- Scenario of Source/Drain Extension and Halo Engineering for High Performance 50nm SOI-pMOSFET
- High-Speed and Low-Power n^+-p^+ Double-Gate SOI CMOS
- Theoretical Study of Alpha-Particle-Induced Soft Errors in Submicron SOI SRAM (Special Issue on ULSI Memory Technology)
- Advanced Input/Output Technology Using Laterally Modulated Channel Metal–Oxide–Semiconductor Field Effect Transistor for 65-nm Node System on a Chip
- High-Speed SOI Bipolar Transistors Using Bonding and Thinning Techniques
- High Frequency Characteristics of Dynamic Threshold-Voltage MOSFET (DTMOS) under Ultra-Low Supply Voltage (Special Issue on Ultra-High-Speed IC and LSI Technology)
- A New SOI-Lateral Bipolar Transistor for High-Speed Operation
- Achieving High Current Gain and Low Emitter Resistance with the SiC_x:F Widegap Emitter
- Sub-2nm Equivalent SiO_2 Thickness Ta_2O_5 for Gate Dielectric Using RTA+UV/O_3
- Impact Ionization in 0.1 μm Metal-Oxide-Semiconductor Field-Effect Transistors
- Current Status and Forecast in High-Performance CMOS Device Technology
- Oxynitride Pad LOCOS (ON-LOCOS) Isolation Technology for Gigabit DRAMs
- New Method of Extracting Inversion Layer Thickness and Charge Profile and Its Impact on Scaled MOSFETs
- Report on the 2001 Symposium on VLSI Technology
- Si Wafer Bonding with Ta Silicide Formation
- Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide