SATOH Akira | FUJITSU LABORATORIES LTD.

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著作論文

Sb Multiple Ion Implanted Channel for Low V_, Deep Submicron SOI-pMOSFETs
Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide
Vth Rolloff Free Sub 0.1μm SOI MOSFETs Using Counter Doping into a Uniformly and Heavily Doped Channel Region
Thermal Budget for Fabricating A Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide
Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide

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