KOJIMA Manabu | Fujitsu Laboratories Ltd.
スポンサーリンク
概要
関連著者
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KOJIMA Manabu
Fujitsu Laboratories Ltd.
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SUGII Toshihiro
FUJITSU LABORATORIES LTD.
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Kojima Miki
Eda Application Engineering Worldwide Development Application Specific Products Tsukuba Technology C
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Nara Yasuo
Fujitsu Laboratories Ltd.
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ARIMOTO Yoshihiro
Fujitsu Laboratories Ltd.
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Fukano Tetsu
FUJITSU LABORATORIES LTD.
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Sugii T
Fujitsr Ltd. Akiruno-shi Jpn
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ARIMOTO Yoshihiro
System LSI Development Labs., FUJITSU LABORATORIES LTD.
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Fukuroda Atsushi
FUJITSU LABORATORIES LTD.
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Arimoto Y
System Lsi Development Labs. Fujitsu Laboratories Ltd.
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HORIGUCHI Naoto
Fujitsu Laboratories Ltd.
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Higaki Naoshi
Fujitsu Laboratories Ltd.
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ITO Takashi
Fujitsu Laboratories Ltd.
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Katsumata Ryota
Toshiba Corporation
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YAMAMOTO Tomonari
Fujitsu Ltd.
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Yamazaki Tatsuya
FUJITSU LABORATORIES LTD.
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SUGIZAKI Taro
FUJITSU LABORATOIRES Ltd.
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NAKANISHI Toshiro
FUJITSU LABORATOIRES Ltd.
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Yamamoto Tomonari
Fujitsu Laboratories Ltd.
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TANAKA Tetsu
Fujitsu Laboratories Ltd.
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Satoh Shigeo
Fujitsu Laboratories Ltd.
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Tagawa Yukio
Fujitsu Ltd.
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Tagawa Yukio
Fujitsu Laboratories Ltd.
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MURAKOSHI Atsushi
Toshiba Corporation
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Yamazaki T
Atr Adaptive Communications Research Laboratories:(present Address)communications Research Laborator
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MOMIYAMA Youichi
Fujitsu Laboratories Ltd.
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Ito T
Department Of Chemical Engineering Graduate School Of Engineering Nagoya University
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SUZUKI Hiroshi
Fujitsu Laboratories Ltd.
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Sugii Toshihiro
Fujitsu Laboratories Ltd., 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Katsumata Ryota
Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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Tanaka Tetsu
Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-0197, Japan
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Yoshida Eiji
Fujitsu Laboratories Ltd., 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Nara Yasuo
Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-0197, Japan
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Hasegawa Nobumasa
Fujitsu Laboratories Ltd., 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Momiyama Youichi
Fujitsu Ltd., 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
著作論文
- Scenario of Source/Drain Extension and Halo Engineering for High Performance 50nm SOI-pMOSFET
- Advanced Input/Output Technology Using Laterally Modulated Channel Metal–Oxide–Semiconductor Field Effect Transistor for 65-nm Node System on a Chip
- High-Speed SOI Bipolar Transistors Using Bonding and Thinning Techniques
- A New SOI-Lateral Bipolar Transistor for High-Speed Operation
- Trap Assisted Leakage Mechanism of 'worst' Junction in Giga-bit DRAM Using Negative Word-Line Voltage
- Highly Reliable Dynamic Random Access Memory Technology for Application Specific Memory with Dual Nitrogen Concentration Gate Oxynitrides Using Selective Nitrogen Implantation