Satoh Shigeo | Fujitsu Laboratories Ltd.

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概要

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著作論文

Analysis and modeling of size dependent mobility enhancement due to mechanical stress
Dopant Profile Design Methodology for 65nm Generation via Inverse Modeling
Scaling Trends and Mitigation Techniques for Soft Errors in Flip-Flops
Scaling Law for Secondary Cosmic-Ray Neutron-Induced Soft-Errors in DRAMs
Impact of Current Gain Increment Effect on Alpha Particle Induced Soft Errors in SOI DRAMs
Theoretical Study of Alpha-Particle-Induced Soft Errors in Submicron SOI SRAM (Special Issue on ULSI Memory Technology)
Novel Soft Error Hardened Latches and Flip-Flops
Neutron-induced Soft-Error Simulation Technology for Logic Circuits
Advanced Input/Output Technology Using Laterally Modulated Channel Metal–Oxide–Semiconductor Field Effect Transistor for 65-nm Node System on a Chip
Analytical Models for Symmetric Thin-Film Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistors
Soft Error Hardened Latch and Its Estimation Method
Neutron-Induced Soft-Error Simulation Technology for Logic Circuits
Technological Trends of Soft Error Estimation Based on Accurate Estimation Method
Mechanical Stress Evaluation of Si Metal--Oxide--Semiconductor Field-Effect Transistor Structure Using Polarized Ultraviolet Raman Spectroscopy Measurements and Calibrated Technology-Computer-Aided-Design Simulations
Potential of and Issues with Multiple-Stressor Technology in High-Performance 45 nm Generation Devices
Impact of Parasitic Bipolar Effect on Single-Event Upset in p-Type Metal--Oxide--Semiconductor Field Effect Transistor with Embedded SiGe

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