UEMURA Taiki | Fujitsu Laboratories Ltd.
スポンサーリンク
概要
関連著者
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UEMURA Taiki
Fujitsu Laboratories Ltd.
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TOSAKA Yoshiharu
Fujitsu Laboratories Ltd.
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Satoh Shigeo
Fujitsu Laboratories Ltd.
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SATOH Shigeo
FUJITSU Ltd.
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TANABE Ryo
Fujitsu Laboratories Ltd.
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MATSUYAMA Hideya
FUJITSU LSI Quality Assurance Div.
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Hatanaka Kichiji
Research Center For Nuclear Physics Osaka University
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TAKAHISA Keiji
Research Center for Nuclear Physics, Osaka University
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HATANAKA Kichiji
Research Center for Nuclear Physics, Osaka University
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Takahisa Keiji
Research Center For Nuclear Physics Osaka University
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MORI Hiroko
FUJITSU LSI Quality Assurance Div.
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Matsuoka Nobuyuki
Research Center For Nuclear Physics Osaka University
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Oka Hideki
Fujitsu Laboratories Ltd
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Satoh Shigeo
Fujitsu Laboratories Ltd., 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Takasu Ryozo
Fujitsu Laboratories Ltd., 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Ehara Hiedo
Fujitsu Ltd., 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Takahisa Keiji
Osaka University, 10-1 Mihogaoka, Ibaraki, Osaka 567-0047, Japan
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Fukuda Mitsuhiro
Osaka University, 10-1 Mihogaoka, Ibaraki, Osaka 567-0047, Japan
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Hatanaka Kichiji
Osaka University, 10-1 Mihogaoka, Ibaraki, Osaka 567-0047, Japan
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Oka Hideki
Fujitsu Laboratories Ltd., 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
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Tosaka Yoshiharu
Fujitsu Microelectronics Ltd., 1500 Mizono, Tado, Kuwana, Mie 511-0192, Japan
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Ikeda Yoshihiro
Fujitsu Semiconductor Ltd., Akiruno Technology Center, Akiruno, Tokyo 197-0833, Japan
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Kato Takashi
Fujitsu Semiconductor Ltd., Akiruno Technology Center, Akiruno, Tokyo 197-0833, Japan
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Suzuki Kaina
Fujitsu Semiconductor Ltd., Akiruno Technology Center, Akiruno, Tokyo 197-0833, Japan
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Mori Hiroko
Fujitsu Semiconductor Ltd., Akiruno Technology Center, Akiruno, Tokyo 197-0833, Japan
著作論文
- Scaling Trends and Mitigation Techniques for Soft Errors in Flip-Flops
- Novel Soft Error Hardened Latches and Flip-Flops
- Neutron-induced Soft-Error Simulation Technology for Logic Circuits
- Robust Flip-Flop Circuit against Soft Errors for Combinational and Sequential Logic Circuits
- Soft Error Hardened Latch and Its Estimation Method
- Neutron-Induced Soft-Error Simulation Technology for Logic Circuits
- Technological Trends of Soft Error Estimation Based on Accurate Estimation Method
- Impact of Parasitic Bipolar Effect on Single-Event Upset in p-Type Metal--Oxide--Semiconductor Field Effect Transistor with Embedded SiGe