Robust Flip-Flop Circuit against Soft Errors for Combinational and Sequential Logic Circuits
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概要
- 論文の詳細を見る
Soft errors in logic circuits are a significant problem in LSIs. We need to consider two phenomena in logic circuits, single-event-upsets (SEUs) which are soft errors in sequential elements, and single-event-transients (SETs) which are soft errors in combinational logic. In this study, we have proposed a robust flip-flop circuit for protecting against SET and SEU problems. This flip-flop mitigates SETs by a low pass filter using a C-element with a delay element. The flip-flop also mitigates SEUs by a multi node latch technique. SEU mitigation efficiencies of the flip-flop are estimated by accelerated alpha particle and neutron experiments. SET mitigation efficiencies of the flip-flop are estimated by simulation. The flip-flop can protect against 99.8% of SEU and 85% of SET with low penalties.
- 2009-04-25
著者
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TOSAKA Yoshiharu
Fujitsu Laboratories Ltd.
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MATSUYAMA Hideya
FUJITSU LSI Quality Assurance Div.
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UEMURA Taiki
Fujitsu Laboratories Ltd.
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Takahisa Keiji
Osaka University, 10-1 Mihogaoka, Ibaraki, Osaka 567-0047, Japan
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Fukuda Mitsuhiro
Osaka University, 10-1 Mihogaoka, Ibaraki, Osaka 567-0047, Japan
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Hatanaka Kichiji
Osaka University, 10-1 Mihogaoka, Ibaraki, Osaka 567-0047, Japan
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Tosaka Yoshiharu
Fujitsu Microelectronics Ltd., 1500 Mizono, Tado, Kuwana, Mie 511-0192, Japan
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