Investigation of Degradation model for Ultra-thin Gate Dielectrics
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概要
- 論文の詳細を見る
- 2004-09-15
著者
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Tamura Naoyoshi
Fujitsu Lab. Ltd. Tokyo Jpn
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Tamura Naoyoshi
Fujitsu Laboratories Ltd.
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MORI Hiroko
FUJITSU LSI Quality Assurance Div.
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EHARA Hideo
FUJITSU LSI Quality Assurance Div.
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KANETA Chioko
FUJITSU Laboratories Ltd.
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MATSUYAMA Hideya
FUJITSU LSI Quality Assurance Div.
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SHONO Ken
FUJITSU LSI Quality Assurance Div.
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Kaneta Chioko
Fujitsu Laboratories Limited
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Tamura Naoyoshi
Fujitsu Lab. Ltd.
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