Generation of a New Interface State Associated with Ultrathin Gate Dielectrics/Silicon under Electric Stress
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概要
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Applying charge pumping, we found a new narrow interface state that was generated above the intrinsic Fermi level in the silicon band gap in ultrathin gate dielectrics/silicon after hot-carrier injection. The width of the structure was about 0.1 eV. There was also a conventional defect structure, $P_{\text{b0}}$, in thin dielectrics. By investigating the correlation between the new structure and $P_{\text{b0}}$, the new structure was found not to originate from $P_{\text{b0}}$. Moreover, by position analysis, the new interface state was found to be generated apart from conventional $P_{\text{b0}}$. Thus, it is possible to obtain information on the new interface state separately. The atomic structure corresponding to the new sharp feature is unclear. However, its appearance could explain why the lifetime results do not meet the traditional model when we tested ultrathin dielectrics.
- 2009-04-25
著者
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MORI Hiroko
FUJITSU LSI Quality Assurance Div.
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MATSUYAMA Hideya
FUJITSU LSI Quality Assurance Div.
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Watanabe Satoru
Fujita Health University
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Mori Hiroko
Fujitsu Microelectronics Ltd., 10-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0197, Japan
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Matsuyama Hideya
Fujitsu Microelectronics Ltd., 10-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0197, Japan
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