Zigzag-HVP : A Cost-effective Technique to Mitigate Soft Errors in Caches with Word-based Access(Processor Architecture)

元データ 2006-11-15 一般社団法人情報処理学会

概要

Error Correction Code (ECC) is widely used to detect and correct soft errors in VLSI caches. Maintaining ECC on a per-word basis, which is preferable in caches with word-based access, is expensive. This paper proposes Zigzag-HVP, a cost-effective technique to detect and correct soft errors in such caches. Zigzag-HVP utilizes horizontal-vertical parity (HVP). HVP maintains the parity of a data array both horizontally and vertically. Basic HVP can detect and correct a single bit error (SBE), but not a multi-bit error (MBE). By dividing the data array into multiple HVP domains and interleaving bits of different domains, a spatial MBE can be converted to multiple SBEs, each of which can be detected and corrected by the corresponding parity domain. Vertical parity updates and error recovery in Zigzag-HVP can be efficiently executed through modifications to the cache data paths, write-buffer, and Built-In Self Test. The evaluation results indicate that the area and power overheads of Zigzag-HVP caches are lower than those of ECC-based ones.

著者

五島 正裕 東京大学情報理工学系研究科
坂井 修一 東京大学 情報理工学系研究科
Goshima Masahiro Graduate School Of Informatics Kyoto University
Hung Luong Graduate School Of Information Science And Technology The University Of Tokyo
Sakai Shuichi Graduate School Of Information Science And Technology The University Of Tokyo

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