3M-7 Reevaluating the Renamed Trace Cache Architecture

元データ 2010-03-08

概要

In order to exploit parallelism, modern superscalar processors utilize register renaming to solve data dependency problems. The RMT(register mapping table) used in register renaming is said to be one of the most energy consuming components in the processor due to its high access frequency and large area. Multi-port structure of the RMT can gain area exponentially to its port number which can make it unrealistic when implementing high width processors. The RTCA, abbreviation for Renamed Trace Cache Architecture(also known as the anti-dualflow architecture) is an architecture proposed to solve these problem that the RMT brings about. Within this architecture, the path between two dependent operand is explicitly shown in order to solve the dependency, that in return can take off the renaming stage of the pipeline. However, extra tags are needed in addition to the trace cache that RCTA uses, which can lead to degradation in performance. In this paper, we evaluate and compare the RCTA to a typical trace cache architecture. It is shown that the increment in trace cache tags can cause an amount of degradation in average fetch IPC. Nevertheless, the shorten pipeline can potentially maintain overall performance.

著者

五島 正裕 東京大学情報理工学系研究科
堀尾 一生 東京大学大学院情報理工学系研究科
坂井 修一 東京大学
塩谷 亮太 東京大学情報理工学系研究科:日本学術振興会
坂井 修一 東京大学 情報理工学系研究科
王 彦鈎 東大
堀尾 一生 東大
塩谷 亮太 東大
五島 正裕 東大
坂井 修一 東大
ハイハー グェン 京都大学情報学研究科

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