Hung Luong | Graduate School Of Information Science And Technology The University Of Tokyo

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概要

• 同名の論文著者
• Graduate School Of Information Science And Technology The University Of Tokyoの論文著者

関連著者

• Hung Luong

  Graduate School Of Information Science And Technology The University Of Tokyo

• Sakai Shuichi

  Graduate School Of Information Science And Technology The University Of Tokyo

• Barli Niko

  Texas Instruments Japan Ltd.

• Iwama Chitaka

  School Of Law The University Of Tokyo

• Tanaka H

  Institute Of Information Security

• Tanaka Hidehiko

  Department Of Bioresources Chemistry Faculty Of Agriculture Okayama University

• Tanaka Hidehiko

  Institute Of Information Security

• SAKAI Shuichi

  Graduate Shool of Information Science and Technology, The University of Tokyo

• BARLI NIKO

  Texas Instruments Japan, Ltd.

• Tanaka Hidehiko

  Graduate School of Electrical Engineering The University of Tokyo

• Tashiro Daisuke

  Hitachi Ltd.

• Takada Masanori

  Graduate School Of Information Science And Technology The University Of Tokyo

• Takada Masanori

  Graduate School Kobe University

• Ge Yi

  Graduate School Of Information Science And Technology The University Of Tokyo

• Ge Y

  東大 大学院情報理工学系研究科

• 葛 毅

  株式会社富士通研究所

• BARLI NIKO

  Graduate School of Information Science and Technology, The University of Tokyo

• IWAMA CHITAKA

  Graduate School of Information Science and Technology, The University of Tokyo

• Yi Ge

  Department of Computer Science

• HUNG LUONG

  Graduate School of Information Science and Technology, the University of Tokyo

• TANAKA Hidehiko

  Institute for Chemical Research, Kyoto University

• Hatta Naoya

  Graduate School Of Engineering Hokkaido University

• 坂井 修一

  東京大学 情報理工学系研究科

• Goshima Masahiro

  Graduate School Of Informatics Kyoto University

• MIURA HIDEYUKI

  Graduate School of Information Science and Technology, The University of Tokyo

• TASHIRO DAISUKE

  Graduate School of Information Science and Technology, The University of Tokyo

• Mine H

  Graduate School Of Information Science And Technology The University Of Tokyo:(present Address)east

• 五島 正裕

  東京大学情報理工学系研究科

• HATTA Naoya

  Graduate School of Engineering, Hokkaido University

• IWAMA CHITAKA

  School of Law, the University of Tokyo

• YANAGAWA YOSHIMITSU

  Engineering Department, The University of Tokyo

• Hatta Naoya

  Graduate School Of Information Science And Technology The University Of Tokyo

• Yanagawa Yoshimitsu

  Engineering Department The University Of Tokyo

• Hatta Naoya

  Graduate School of Information Science and Technology, the University of Tokyo

• GOSHIMA Masahiro

  Graduate School of Information Science and Technology, The University of Tokyo

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著作論文

• Cache Coherence Strategies for Speculative Multithreading CMPs : Characterization and Performance Study(Processor Architecture)
• Bus Serialization for Reducing Power Consumption(Processor Architecture)
• Way-variable Caches for Static Power Reduction (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
• Way-variable Caches for Static Power Reduction
• Complexity Analysis of A Cache Controller for Speculative Multithreading Chip Multiprocessors (「ハイパフォーマンスコンピューティングとアーキテクチャの評価」に関する北海道ワークショップ(HOKKE-2003))
• A Hardware/Sofware Approach for Thread Level Control Speculation (計算機アーキテクチャ研究報告 2002年並列/分散/協調処理に関する『湯布院』サマー・ワークショップ(SWoPP湯布院2002))
• A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits
• A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits
• A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits (デザインガイア2004--VLSI設計の新しい大地を考える研究会)
• A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits (デザインガイア2004--VLSI設計の新しい大地を考える研究会)
• A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits (デザインガイア2004--VLSI設計の新しい大地を考える研究会)
• Dynamic Estimation of Task Level Parallelism with Operating System Support(System Evaluation)
• Dynamic Estimation of Task Level Parallelism with Operating System Support
• Zigzag-HVP : A Cost-effective Technique to Mitigate Soft Errors in Caches with Word-based Access(Processor Architecture)
• Zigzag-HVP: A Cost-effective Technique to Mitigate Soft Errors in Caches with Word-based Access
• Bus Serialization for Reducing Power Consumption
• Bus Serialization for Reducing Power Consumption

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