Bus Serialization for Reducing Power Consumption(Processor Architecture)
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概要
- 論文の詳細を見る
On-chip interconnects are becoming a major power consumer in scaled VLSI design. Consequently, bus power reduction has become effective for total power reduction on chip multiprocessors and system-on-a-chip requiring long interconnects as buses. In this paper, we advocate the use of bus serialization to reduce bus power consumption. Bus serialization decreases the number of wires and increases the pitch between the wires. The wider pitch decreases the coupling capacitances of the wires, and consequently reduces bus power consumption. Evaluation results indicate that our technique can reduce bus power consumption by 30% in the 45 nm technology process.
- 一般社団法人情報処理学会の論文
- 2006-03-15
著者
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TANAKA Hidehiko
Institute for Chemical Research, Kyoto University
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Tanaka H
Institute Of Information Security
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Tanaka Hidehiko
Department Of Bioresources Chemistry Faculty Of Agriculture Okayama University
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Tanaka Hidehiko
Institute Of Information Security
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Hung Luong
Graduate School Of Information Science And Technology The University Of Tokyo
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Tashiro Daisuke
Hitachi Ltd.
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SAKAI Shuichi
Graduate Shool of Information Science and Technology, The University of Tokyo
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Sakai Shuichi
Graduate School Of Information Science And Technology The University Of Tokyo
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HATTA Naoya
Graduate School of Engineering, Hokkaido University
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BARLI NIKO
Texas Instruments Japan, Ltd.
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IWAMA CHITAKA
School of Law, the University of Tokyo
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Barli Niko
Texas Instruments Japan Ltd.
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Hatta Naoya
Graduate School Of Information Science And Technology The University Of Tokyo
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Hatta Naoya
Graduate School Of Engineering Hokkaido University
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Iwama Chitaka
School Of Law The University Of Tokyo
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