Dynamic Estimation of Task Level Parallelism with Operating System Support
スポンサーリンク
概要
- 論文の詳細を見る
The amount of task-level parallelism (TLP) in a runtime workload is useful information for determining the efficient usage of multiprocessors. This paper presents mechanisms for dynamically estimating the amount of TLP in runtime workloads. Modifications are made to the operating system (OS) to collect information about processor utilization and task activities, from which the TLP can be calculated. By effectively utilizing the time stamp counter (TSC) hardware, the task activities can be monitored with fine time resolution, which enables the TLP to be estimated with fine granularity. We implemented the mechanisms on a recent version of Linux. Evaluation results indicate that the mechanisms can estimate the TLP accurately for various workloads. The overheads imposed by the mechanisms are small.
著者
-
Hung Luong
Graduate School Of Information Science And Technology The University Of Tokyo
-
Sakai Shuichi
Graduate School Of Information Science And Technology The University Of Tokyo
関連論文
- Cache Coherence Strategies for Speculative Multithreading CMPs : Characterization and Performance Study(Processor Architecture)
- Associating Semantically Structured Cooking Videos with Their Preparation Steps
- Bus Serialization for Reducing Power Consumption(Processor Architecture)
- Way-variable Caches for Static Power Reduction (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
- Way-variable Caches for Static Power Reduction
- Complexity Analysis of A Cache Controller for Speculative Multithreading Chip Multiprocessors (「ハイパフォーマンスコンピューティングとアーキテクチャの評価」に関する北海道ワークショップ(HOKKE-2003))
- A Hardware/Sofware Approach for Thread Level Control Speculation (計算機アーキテクチャ研究報告 2002年並列/分散/協調処理に関する『湯布院』サマー・ワークショップ(SWoPP湯布院2002))
- Dynamic Thread Extension for Speculative Multithreading Architectur (計算機アーキテクチャ 研究報告 2001年並列/分散/協調処理に関する『沖縄』サマー・ワークショップ(SWoPP「沖縄」2001)--研究会・連続同時開催--テーマ:並列/分散/協調システムの支援アーキテクチャ技術と評価)
- A Thread Partitioning Algorithm using Structural Analysis (計算機アーキテクチャ 研究報告 2000年並列/分散/協調処理に開する『松山』サマー・ワークショップ(SWoPP「松山」2000)--研究会・連続同時開催 テーマ:並列/分散/協調システムの支援アーキテクチャ技術と評価)
- Low-Overhead Architecture for Security Tag
- A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits
- A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits
- A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits (デザインガイア2004--VLSI設計の新しい大地を考える研究会)
- A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits (デザインガイア2004--VLSI設計の新しい大地を考える研究会)
- A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits (デザインガイア2004--VLSI設計の新しい大地を考える研究会)
- Musical Part Separation Based on Perceptual Hierarchy
- VLDP Multipath Execution: Mechanism and Evaluations (計算機アーキテクチャ 研究報告 2001年並列/分散/協調処理に関する『沖縄』サマー・ワークショップ(SWoPP「沖縄」2001)--研究会・連続同時開催--テーマ:並列/分散/協調システムの支援アーキテクチャ技術と評価)
- Delay-Compensation Flip-Flops for Timing-Error Tolerant Circuit Design
- Ultra Dependable Processor
- Dynamic Estimation of Task Level Parallelism with Operating System Support(System Evaluation)
- Dynamic Estimation of Task Level Parallelism with Operating System Support
- Zigzag-HVP : A Cost-effective Technique to Mitigate Soft Errors in Caches with Word-based Access(Processor Architecture)
- Delay-Compensation Flip-Flop with In-situ Error Monitoring for Low-Power and Timing-Error-Tolerant Circuit Design
- Zigzag-HVP: A Cost-effective Technique to Mitigate Soft Errors in Caches with Word-based Access
- Register Indirect Jump Target Forwarding
- Bus Serialization for Reducing Power Consumption
- Bus Serialization for Reducing Power Consumption
- Register Indirect Jump Target Forwarding