Cache Coherence Strategies for Speculative Multithreading CMPs : Characterization and Performance Study(Processor Architecture)

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概要

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• Thread-level memory speculation is one of speculation techniques usually employed in speculative multithreading architectures. On shared-bus chip multiprocessors (CMPs), the technique can be implemented by extending their cache coherence mechanisms. Several implementations have been proposed and evaluated. However, there is no study that compares the impact of the taken strategies and identifies which of the strategies are important. In this paper, we first characterize the effect of speculative multithreading executions to cache misses. We find that sharing misses occupy the largest portion of misses, and spreading accesses in speculative multithreading executions cause a significant increase in the miss rate. Then, we perform a performance study of several cache coherence strategies. 0ur study shows that update-based protocols, which do not suffer from sharing misses, achieve significantly higher performance than invalidation-based protocols. The study also reveals that applying a modified read-broadcast (snarfing) approach is effective for suppressing the effect of spreading cache accesses. Finally, the study shows that managing the exclusivity of data in caches offers little performance improvement.

• 2004-10-15

著者

• Tanaka H

  Institute Of Information Security

• Tanaka Hidehiko

  Department Of Bioresources Chemistry Faculty Of Agriculture Okayama University

• Tanaka Hidehiko

  Institute Of Information Security

• Hung Luong

  Graduate School Of Information Science And Technology The University Of Tokyo

• Tanaka Hidehiko

  Graduate School of Electrical Engineering The University of Tokyo

• Tashiro Daisuke

  Hitachi Ltd.

• SAKAI Shuichi

  Graduate Shool of Information Science and Technology, The University of Tokyo

• Sakai Shuichi

  Graduate School Of Information Science And Technology The University Of Tokyo

• BARLI NIKO

  Texas Instruments Japan, Ltd.

• BARLI NIKO

  Graduate School of Information Science and Technology, The University of Tokyo

• MIURA HIDEYUKI

  Graduate School of Information Science and Technology, The University of Tokyo

• IWAMA CHITAKA

  Graduate School of Information Science and Technology, The University of Tokyo

• TASHIRO DAISUKE

  Graduate School of Information Science and Technology, The University of Tokyo

• Barli Niko

  Texas Instruments Japan Ltd.

• Iwama Chitaka

  School Of Law The University Of Tokyo

• Mine H

  Graduate School Of Information Science And Technology The University Of Tokyo:(present Address)east

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