Bus Serialization for Reducing Power Consumption

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概要

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• On-chip interconnects are becoming a major power consumer in scaled VLSI design. Consequently, bus power reduction has become effective for total power reduction on chip multiprocessors and system-on-a-chip requiring long interconnects as buses. In this paper, we advocate the use of bus serialization to reduce bus power consumption. Bus serialization decreases the number of wires and increases the pitch between the wires. The wider pitch decreases the coupling capacitances of the wires, and consequently reduces bus power consumption. Evaluation results indicate that our technique can reduce bus power consumption by 30% in the 45nm technology process.

• Information and Media Technologies 編集運営会議の論文

著者

• TANAKA Hidehiko

  Institute for Chemical Research, Kyoto University

• Hung Luong

  Graduate School Of Information Science And Technology The University Of Tokyo

• Tashiro Daisuke

  Hitachi Ltd.

• Sakai Shuichi

  Graduate School Of Information Science And Technology The University Of Tokyo

• Barli Niko

  Texas Instruments Japan Ltd.

• Hatta Naoya

  Graduate School Of Engineering Hokkaido University

• Iwama Chitaka

  School Of Law The University Of Tokyo

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