The Design of PRESTO: A Framework For Architecture Level Power Estimation (2003年並列/分散/協調処理に関する『松江』サマー・ワークショップ(SWoPP松江2003)研究会・連続同時開催)

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概要

• 論文の詳細を見る

• This paper presents PRESTO, a framework for architecture level power estimation. To enable flexible adaptation to various hardware designs, PRESTO separates power model of a hardware structure into three different layers: technology layer, circuit layer and dynamic behavior layer. Furthermore, to increase software reusability, circuit models are built using a hierarchical approach. This paper explains the design of PRESTO and presents validation results of analytical power models for logic gates and SRAM structure. A case study in which PRESTO is used to evaluate an architecture level power reduction technique for caches is also described.

• 一般社団法人情報処理学会の論文
• 2003-08-05

著者

• Tanaka H

  Institute Of Information Security

• Tanaka Hidehiko

  Department Of Bioresources Chemistry Faculty Of Agriculture Okayama University

• Tanaka Hidehiko

  Institute Of Information Security

• BARLI NIKO

  Texas Instruments Japan, Ltd.

• Barli Niko

  Texas Instruments Japan Ltd.

• Iwama Chitaka

  School Of Law The University Of Tokyo

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