Barli Niko | Texas Instruments Japan Ltd.

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概要

• 同名の論文著者
• Texas Instruments Japan Ltd.の論文著者

関連著者

• Barli Niko

  Texas Instruments Japan Ltd.

• Tanaka H

  Institute Of Information Security

• Tanaka Hidehiko

  Department Of Bioresources Chemistry Faculty Of Agriculture Okayama University

• Tanaka Hidehiko

  Institute Of Information Security

• Sakai Shuichi

  Graduate School Of Information Science And Technology The University Of Tokyo

• BARLI NIKO

  Texas Instruments Japan, Ltd.

• Iwama Chitaka

  School Of Law The University Of Tokyo

• Hung Luong

  Graduate School Of Information Science And Technology The University Of Tokyo

• SAKAI Shuichi

  Graduate Shool of Information Science and Technology, The University of Tokyo

• Tanaka Hidehiko

  Graduate School of Electrical Engineering The University of Tokyo

• Tashiro Daisuke

  Hitachi Ltd.

• BARLI NIKO

  Graduate School of Information Science and Technology, The University of Tokyo

• IWAMA CHITAKA

  Graduate School of Information Science and Technology, The University of Tokyo

• TANAKA Hidehiko

  Institute for Chemical Research, Kyoto University

• TASHIRO DAISUKE

  Graduate School of Information Science and Technology, The University of Tokyo

• Hatta Naoya

  Graduate School Of Engineering Hokkaido University

• MIURA HIDEYUKI

  Graduate School of Information Science and Technology, The University of Tokyo

• Hatta Naoya

  Graduate School Of Information Science And Technology The University Of Tokyo

• Mine H

  Graduate School Of Information Science And Technology The University Of Tokyo:(present Address)east

• Mine Hiroshi

  Graduate School Of Engineering University Of Tokyo

• HATTA Naoya

  Graduate School of Engineering, Hokkaido University

• IWAMA CHITAKA

  School of Law, the University of Tokyo

• HATTA NAOYA

  東京大学

• BARLI NIKO

  日本テキサス・インスツルメンツ

• IWAMA CHITAKA

  東京大学

• HUNG LUONG

  東京大学

• TASHIRO DAISUKE

  東京大学

• SAKA SHUICHI

  東京大学

• TANAKA HIDEHIKO

  情報セキュリティ大学院大学

• YANAGAWA YOSHIMITSU

  Engineering Department, The University of Tokyo

• Yanagawa Yoshimitsu

  Engineering Department The University Of Tokyo

• 峯 博史

  Graduate School of Engineering, University of Tokyo

• 坂井 修一

  Graduate School of Engineering, University of Tokyo

• Hatta Naoya

  Graduate School of Information Science and Technology, the University of Tokyo

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著作論文

• Cache Coherence Strategies for Speculative Multithreading CMPs : Characterization and Performance Study(Processor Architecture)
• Bus Serialization for Reducing Power Consumption(Processor Architecture)
• Bus Serialization for Reducing Power Consumption
• Way-variable Caches for Static Power Reduction (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
• Way-variable Caches for Static Power Reduction
• The Design of PRESTO: A Framework For Architecture Level Power Estimation (2003年並列/分散/協調処理に関する『松江』サマー・ワークショップ(SWoPP松江2003)研究会・連続同時開催)
• Complexity Analysis of A Cache Controller for Speculative Multithreading Chip Multiprocessors (「ハイパフォーマンスコンピューティングとアーキテクチャの評価」に関する北海道ワークショップ(HOKKE-2003))
• A Hardware/Sofware Approach for Thread Level Control Speculation (計算機アーキテクチャ研究報告 2002年並列/分散/協調処理に関する『湯布院』サマー・ワークショップ(SWoPP湯布院2002))
• Dynamic Thread Extension for Speculative Multithreading Architectur (計算機アーキテクチャ 研究報告 2001年並列/分散/協調処理に関する『沖縄』サマー・ワークショップ(SWoPP「沖縄」2001)--研究会・連続同時開催--テーマ:並列/分散/協調システムの支援アーキテクチャ技術と評価)
• A Thread Partitioning Algorithm using Structural Analysis (計算機アーキテクチャ 研究報告 2000年並列/分散/協調処理に開する『松山』サマー・ワークショップ(SWoPP「松山」2000)--研究会・連続同時開催 テーマ:並列/分散/協調システムの支援アーキテクチャ技術と評価)
• Bus Serialization for Reducing Power Consumption
• Bus Serialization for Reducing Power Consumption

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