Way-variable Caches for Static Power Reduction (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
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概要
- 論文の詳細を見る
Power consumption due to leakage increases rapidly as devices scale to smaller geometries. We propose way-variable caches that dynamically adapt the number of active ways according to runtime requirements. By entirely gating the unused ways from the voltage supply, the leakage can be significantly reduced. We then apply an original algorithm utilizing data access locality to make proper resizing decisions. Performance evaluations are done with a superscalar processor model having 16-KB, 4-way set-associative L1 instruction and data caches. The results verified that, on average, 1.7 ways of the instruction cache can be disabled with only 1.3% performance degradation in the case of instruction cache. The values are 1.5 ways and 1.1% in the case of the data cache.
- 一般社団法人情報処理学会の論文
- 2003-11-27
著者
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Tanaka H
Institute Of Information Security
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Tanaka Hidehiko
Department Of Bioresources Chemistry Faculty Of Agriculture Okayama University
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Tanaka Hidehiko
Institute Of Information Security
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Hung Luong
Graduate School Of Information Science And Technology The University Of Tokyo
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Tanaka Hidehiko
Graduate School of Electrical Engineering The University of Tokyo
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SAKAI Shuichi
Graduate Shool of Information Science and Technology, The University of Tokyo
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Sakai Shuichi
Graduate School Of Information Science And Technology The University Of Tokyo
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BARLI NIKO
Texas Instruments Japan, Ltd.
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BARLI NIKO
Graduate School of Information Science and Technology, The University of Tokyo
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IWAMA CHITAKA
Graduate School of Information Science and Technology, The University of Tokyo
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Barli Niko
Texas Instruments Japan Ltd.
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Iwama Chitaka
School Of Law The University Of Tokyo
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