VLDP Multipath Execution: Mechanism and Evaluations (計算機アーキテクチャ 研究報告 2001年並列/分散/協調処理に関する『沖縄』サマー・ワークショップ(SWoPP「沖縄」2001)--研究会・連続同時開催--テーマ:並列/分散/協調システムの支援アーキテクチャ技術と評価)

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概要

• 論文の詳細を見る

• This paper studies and explores cost-effective execution mechanism for VLDP : a new microprocessor architecture, which performs multipath excution on a large number of excution units with distributed registers. Special attention is payed on current development of the interconnection network for distributed register communication. Trace-driven simulations are performed to quantitatively evaluate the execution mechanism.

• 一般社団法人情報処理学会の論文
• 2001-07-25

著者

• Hattori Naoya

  Graduate Shcool Of Information Science And Technology The University Of Tokyo

• Tanaka Hidehiko

  Graduate School of Electrical Engineering The University of Tokyo

• Tanaka Hidehiko

  Graduate Shcool Of Information Science And Technology The University Of Tokyo

• Sakai Shuichi

  Graduate School Of Information Science And Technology The University Of Tokyo

• Sakai Shuichi

  Graduate Shcool Of Information Science And Technology The University Of Tokyo

• LI SHENGYING

  Graduate School of Engineering, The University of Tokyo

• AJIMA YUICHIRO

  Graduate School of Engineering, The University of Tokyo

• Li Shengying

  Graduate School Of Engineering The University Of Tokyo

• Ajima Yuichiro

  Graduate School Of Engineering The University Of Tokyo

• 李 盛穎

  Graduate School of Engineering, The University of Tokyo

• 服部 直也

  Graduate Shcool of Information Science and Technology, The University of Tokyo

• 安島 雄一郎

  Graduate School of Engineering, The University of Tokyo

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