A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits (デザインガイア2004--VLSI設計の新しい大地を考える研究会)

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概要

• 論文の詳細を見る

• The soft error rates (SER) in logic circuits increase quickly as devices scale. Existing techniques to mitigate soft errors hi logic circuits often incur large overheads. In this work, we propose a 'lightweight' technique that detects soft errors in logic circuits, utilizing the concept of temporal sampling. The technique adds some modifications to the conventional pipeline to allow data to be sampled twice in time and compared for integrity. The area, power, and tuning overheads of modifying a 32-bit multiplier to support the technique are respectively 19.3%, 7.6%, and 6.4%. Comparing to existing soft error detection circuit techniques, our technique incurs lower overheads. The technique is also applicable in scaled process technologies.

• 社団法人電子情報通信学会の論文
• 2004-11-24

著者

• Hung Luong

  Graduate School Of Information Science And Technology The University Of Tokyo

• Takada Masanori

  Graduate School Of Information Science And Technology The University Of Tokyo

• Takada Masanori

  Graduate School Kobe University

• Ge Yi

  Graduate School Of Information Science And Technology The University Of Tokyo

• Ge Y

  東大 大学院情報理工学系研究科

• Sakai Shuichi

  Graduate School Of Information Science And Technology The University Of Tokyo

• 葛 毅

  株式会社富士通研究所

• Yi Ge

  Department of Computer Science

• HUNG LUONG

  Graduate School of Information Science and Technology, the University of Tokyo

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