数値制御プラズマCVM (Chemical Vaporization Machining)によるSOIの薄膜化 : デバイス用基板としての加工面の評価

概要

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The trial manufacture of the ultra-thin SOI (Silicon on Insulator) wafer has already been carried out by numerically controlled plasma CVM (Chemical Vaporization Machining). In this paper, it is evaluated whether the wafer machined by plasma CVM can use as a substrate for a semiconductor integrated circuit. Though metal contamination and some particles are brought in the machining, it has been confirmed that they are removed by usual wet cleaning after the machining. The characteristic of the MOS diode formed on the machined wafer and the reference wafer is evaluated, and it is shown that both characteristics are equivalent, Furthermore, the I_D-V_G characteristic of the MOSFET formed on the machined SOI wafer and the reference SOI wafer is compared, and it is shown that both characteristics are also equivalent. That is to say, in has been concluded that the wafer machined by plasma CVM is usable as a substrate for a semiconductor integrated circuit.
社団法人精密工学会の論文
2003-05-05